{"id":2223487,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223487/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415111738.3264448-1-andrew@rail5.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415111738.3264448-1-andrew@rail5.org>","list_archive_url":null,"date":"2026-04-15T11:17:07","name":"target/loongarch: Fix SWI interrupt delivery via CSR_ESTAT","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bbe76a24dc2ef1e70426d249719b33cadc367776","submitter":{"id":71296,"url":"http://patchwork.ozlabs.org/api/1.2/people/71296/?format=json","name":"Andrew S. Rightenburg\" via qemu development","email":"qemu-devel@nongnu.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415111738.3264448-1-andrew@rail5.org/mbox/","series":[{"id":499974,"url":"http://patchwork.ozlabs.org/api/1.2/series/499974/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499974","date":"2026-04-15T11:17:07","name":"target/loongarch: Fix SWI interrupt delivery via CSR_ESTAT","version":1,"mbox":"http://patchwork.ozlabs.org/series/499974/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223487/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223487/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=temperror header.d=rail5.org header.i=@rail5.org header.a=rsa-sha256\n header.s=mail header.b=RAAYM8P0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwdvQ1Fs4z1yDF\n\tfor ; Wed, 15 Apr 2026 21:19:12 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCyGL-0000Dv-ES; Wed, 15 Apr 2026 07:18:30 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wCyGG-0000DH-DR\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 07:18:24 -0400","from layka.disroot.org ([178.21.23.139])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from ) id 1wCyGE-00018c-IV\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 07:18:23 -0400","from [127.0.0.1] (localhost [127.0.0.1])\n by disroot.org (Postfix) with ESMTP id 88CC72650C;\n Wed, 15 Apr 2026 13:18:16 +0200 (CEST)","from layka.disroot.org ([127.0.0.1])\n by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id 6tAwmskDO1UY; Wed, 15 Apr 2026 13:18:16 +0200 (CEST)"],"X-Virus-Scanned":"SPAM Filter at disroot.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=rail5.org; s=mail;\n t=1776251896; bh=UR6UQSfqlww9S8q5dRVffbCW+mZBwQCATEBpNojYDmY=;\n h=From:To:Cc:Subject:Date;\n b=RAAYM8P0KPgqOFlzhDR8ld7+N3gNZHoyEqbW0UOpxt+PEJ174DsXU+/88b2r7SJ5h\n EIoIUPGCw+ExlGAa/XfIM0UhXl4Id0uJx8PgnkyJynpZsb1BE3sDTihYo1NlYEdkU0\n tTJqdAcZBswB1AEfxTNBDcX/mfrGIWpzQWZp6FYEV4BZxNmQWDVqVG4A/VRcBEatpN\n rWQqBBEqOXM4A924YF/6KIWXWZg7eyThyv2ww8/7O+QSrteZmkdmNw4Ct9wCH656W6\n dqCZNK5FKdloGQC3fXdtq/NGht5bgWJaz/mOy8AJq7JdU8cNLJyiufkZZuyXRKwu6K\n 92reBbsiukKDg==","To":"qemu-devel@nongnu.org","Cc":"Song Gao , \"Andrew S. Rightenburg\" ","Subject":"[PATCH] target/loongarch: Fix SWI interrupt delivery via CSR_ESTAT","Date":"Wed, 15 Apr 2026 19:17:07 +0800","Message-ID":"<20260415111738.3264448-1-andrew@rail5.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=178.21.23.139; envelope-from=andrew@rail5.org;\n helo=layka.disroot.org","X-Spam_score_int":"-16","X-Spam_score":"-1.7","X-Spam_bar":"-","X-Spam_report":"(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1,\n DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-to":"\"Andrew S. Rightenburg\" ","From":"\"Andrew S. Rightenburg\" via qemu development ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"In TCG mode, helper_csrwr_estat() updates CSR.ESTAT.IS[1:0] (SWI0/SWI1)\nwhen the guest writes CSR_ESTAT, but it did not update the CPU interrupt\nrequest state. As a result, software interrupts could be observed as pending\nin CSR.ESTAT while no interrupt exception was taken.\n\nUpdate CPU_INTERRUPT_HARD after modifying CSR_ESTAT, matching the behavior of\nloongarch_cpu_set_irq(). The helper runs without the Big QEMU Lock (BQL), so\ntake the BQL while calling cpu_interrupt().\n\nFixes: 5b1dedfe848b (\"target/loongarch: Add LoongArch CSR instruction\")\nReported-by: Andrew S. Rightenburg \nSigned-off-by: Andrew S. Rightenburg \n---\n target/loongarch/tcg/csr_helper.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)","diff":"diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c\nindex cd35ca93c7..0a5ed52eb6 100644\n--- a/target/loongarch/tcg/csr_helper.c\n+++ b/target/loongarch/tcg/csr_helper.c\n@@ -98,10 +98,22 @@ target_ulong helper_csrrd_msgir(CPULoongArchState *env)\n target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)\n {\n int64_t old_v = env->CSR_ESTAT;\n+ CPUState *cs = env_cpu(env);\n \n /* Only IS[1:0] can be written */\n env->CSR_ESTAT = deposit64(env->CSR_ESTAT, 0, 2, val);\n \n+ /*\n+ * Software interrupts (SWI0/SWI1) are latched in CSR.ESTAT.IS[1:0].\n+ * Make sure the CPU interrupt request state tracks the pending bits,\n+ * matching the behavior of loongarch_cpu_set_irq().\n+ */\n+ if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {\n+ bql_lock();\n+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);\n+ bql_unlock();\n+ }\n+\n return old_v;\n }\n \n","prefixes":[]}