{"id":2223474,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223474/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-32-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-32-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:52","name":"[v4,31/31] hw/arm/smmuv3: Add cmdqv property for SMMUv3 device","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"84a3dbcd417c8b819472598f94f66e4db66443a9","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-32-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223474/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223474/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=OfNhjxh4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BL02EPF00021F6F.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MW4PR12MB7468","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Introduce a \"cmdqv\" property to enable Tegra241 CMDQV support.\nThis is only enabled for accelerated SMMUv3 devices.\n\nReviewed-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/smmuv3.c | 7 +++++++\n 1 file changed, 7 insertions(+)","diff":"diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex c9ff6298f5..51b7d01da5 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1993,6 +1993,10 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"ssidsize can only be set if accel=on\");\n return false;\n }\n+ if (s->cmdqv == ON_OFF_AUTO_ON) {\n+ error_setg(errp, \"cmdqv can only be enabled if accel=on\");\n+ return false;\n+ }\n return true;\n }\n \n@@ -2161,6 +2165,7 @@ static const Property smmuv3_properties[] = {\n DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_AUTO),\n DEFINE_PROP_SSIDSIZE_MODE(\"ssidsize\", SMMUv3State, ssidsize,\n SSID_SIZE_MODE_AUTO),\n+ DEFINE_PROP_ON_OFF_AUTO(\"cmdqv\", SMMUv3State, cmdqv, ON_OFF_AUTO_AUTO),\n };\n \n static void smmuv3_instance_init(Object *obj)\n@@ -2200,6 +2205,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Valid range is 0-20, where 0 disables SubstreamID support. \"\n \"Defaults to auto. A value greater than 0 is required to enable \"\n \"PASID support.\");\n+ object_class_property_set_description(klass, \"cmdqv\",\n+ \"Enable/disable CMDQ-Virtualisation support (for accel=on)\");\n }\n \n static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,\n","prefixes":["v4","31/31"]}