{"id":2223466,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223466/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-4-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-4-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:24","name":"[v4,03/31] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d0aee5a8c93fe87d8b3114c135041c0773cfc1c2","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-4-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223466/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223466/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ZiyzNEWL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3E.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"IA1PR12MB6530","X-Spam_score_int":"-25","X-Spam_score":"-2.6","X-Spam_bar":"--","X-Spam_report":"(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nAdd a helper to allocate an iommufd backed HW queue for a vIOMMU.\n\nWhile at it, define a struct IOMMUFDHWqueue for use by vendor\nimplementations.\n\nSigned-off-by: Nicolin Chen \nReviewed-by: Eric Auger \nSigned-off-by: Shameer Kolothum \n---\n include/system/iommufd.h | 11 +++++++++++\n backends/iommufd.c | 31 +++++++++++++++++++++++++++++++\n backends/trace-events | 1 +\n 3 files changed, 43 insertions(+)","diff":"diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex e027800c91..8009ce3d31 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -65,6 +65,12 @@ typedef struct IOMMUFDVeventq {\n bool event_start; /* True after first valid event; cleared on overflow */\n } IOMMUFDVeventq;\n \n+/* HW queue object for a vIOMMU-specific HW-accelerated queue */\n+typedef struct IOMMUFDHWqueue {\n+ IOMMUFDViommu *viommu;\n+ uint32_t hw_queue_id;\n+} IOMMUFDHWqueue;\n+\n bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp);\n void iommufd_backend_disconnect(IOMMUFDBackend *be);\n \n@@ -101,6 +107,11 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n uint32_t *out_veventq_id,\n uint32_t *out_veventq_fd, Error **errp);\n \n+bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id,\n+ uint32_t queue_type, uint32_t index,\n+ uint64_t addr, uint64_t length,\n+ uint32_t *out_hw_queue_id, Error **errp);\n+\n bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_id,\n bool start, Error **errp);\n bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id,\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex 9b07ac19c2..3be7b07eec 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -556,6 +556,37 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n return true;\n }\n \n+bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id,\n+ uint32_t queue_type, uint32_t index,\n+ uint64_t addr, uint64_t length,\n+ uint32_t *out_hw_queue_id, Error **errp)\n+{\n+ int ret;\n+ struct iommu_hw_queue_alloc alloc_hw_queue = {\n+ .size = sizeof(alloc_hw_queue),\n+ .flags = 0,\n+ .viommu_id = viommu_id,\n+ .type = queue_type,\n+ .index = index,\n+ .nesting_parent_iova = addr,\n+ .length = length,\n+ };\n+\n+ ret = ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue);\n+\n+ trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type,\n+ index, addr, length,\n+ alloc_hw_queue.out_hw_queue_id, ret);\n+ if (ret) {\n+ error_setg_errno(errp, errno, \"IOMMU_HW_QUEUE_ALLOC failed\");\n+ return false;\n+ }\n+\n+ g_assert(out_hw_queue_id);\n+ *out_hw_queue_id = alloc_hw_queue.out_hw_queue_id;\n+ return true;\n+}\n+\n bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n uint32_t hwpt_id, Error **errp)\n {\ndiff --git a/backends/trace-events b/backends/trace-events\nindex 3ba0c3503c..c5c1d95aad 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_type, u\n iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id, int ret) \" iommufd=%d type=%u dev_id=%u hwpt_id=%u data_ptr=0x%\"PRIx64\" data_len=0x%x viommu_id=%u (%d)\"\n iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_id, uint64_t virt_id, uint32_t vdev_id, int ret) \" iommufd=%d dev_id=%u viommu_id=%u virt_id=0x%\"PRIx64\" vdev_id=%u (%d)\"\n iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type, uint32_t veventq_id, uint32_t veventq_fd, int ret) \" iommufd=%d viommu_id=%u type=%u veventq_id=%u veventq_fd=%u (%d)\"\n+iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t queue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id, int ret) \" iommufd=%d viommu_id=%u queue_type=%u index=%u addr=0x%\"PRIx64\" size=0x%\"PRIx64\" queue_id=%u (%d)\"\n \n # igvm-cfg.c\n igvm_reset_enter(int type) \"type=%u\"\n","prefixes":["v4","03/31"]}