{"id":2223462,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223462/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-14-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-14-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:34","name":"[v4,13/31] hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ad43cef100215e6e72f23989a97782ec0ff4b4b4","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-14-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223462/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223462/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=shbxpAZ/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3E.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MN6PR12MB8567","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nReplace the stub implementation with real vIOMMU allocation for\nTegra241 CMDQV.\n\nAllocate a matching vEVENTQ together with the vIOMMU, since it is\nspecific to the Tegra241 CMDQV vIOMMU and used to receive CMDQV\nevents.\n\nFree both objects on teardown.\n\nSigned-off-by: Nicolin Chen \nCo-developed-by: Shameer Kolothum \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.h | 1 +\n hw/arm/tegra241-cmdqv.c | 46 ++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 46 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 2a34a4b6b4..fa0aa3ab04 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -30,6 +30,7 @@ typedef struct Tegra241CMDQV {\n SMMUv3AccelState *s_accel;\n MemoryRegion mmio_cmdqv;\n qemu_irq irq;\n+ IOMMUFDVeventq *veventq;\n } Tegra241CMDQV;\n \n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex ccd3c6d275..2f1084b55f 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -25,13 +25,57 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t value,\n \n static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n {\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDViommu *viommu = accel->viommu;\n+ Tegra241CMDQV *cmdqv = accel->cmdqv;\n+ IOMMUFDVeventq *veventq = cmdqv->veventq;\n+\n+ if (!viommu) {\n+ return;\n+ }\n+ if (veventq) {\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ cmdqv->veventq = NULL;\n+ }\n+ iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id);\n }\n \n static bool\n tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n uint32_t *out_viommu_id, Error **errp)\n {\n- error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n+ Tegra241CMDQV *cmdqv = s->s_accel->cmdqv;\n+ uint32_t viommu_id, veventq_id, veventq_fd;\n+ IOMMUFDVeventq *veventq;\n+\n+ if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,\n+ IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV,\n+ idev->hwpt_id, &cmdqv->cmdqv_data,\n+ sizeof(cmdqv->cmdqv_data), &viommu_id,\n+ errp)) {\n+ return false;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(idev->iommufd, viommu_id,\n+ IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV,\n+ 1 << 16, &veventq_id, &veventq_fd,\n+ errp)) {\n+ error_append_hint(errp, \"Tegra241 CMDQV: failed to alloc veventq\");\n+ goto free_viommu;\n+ }\n+\n+ veventq = g_new(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ cmdqv->veventq = veventq;\n+\n+ *out_viommu_id = viommu_id;\n+ return true;\n+\n+free_viommu:\n+ iommufd_backend_free_id(idev->iommufd, viommu_id);\n return false;\n }\n \n","prefixes":["v4","13/31"]}