{"id":2223461,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223461/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-2-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-2-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:22","name":"[v4,01/31] backends/iommufd: Update iommufd_backend_get_device_info","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3f39dd811e0edc5d614a900b22e6f4e2a680b243","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-2-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223461/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223461/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=j+DnZ7MS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3E.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"IA1PR12MB6530","X-Spam_score_int":"-25","X-Spam_score":"-2.6","X-Spam_bar":"--","X-Spam_report":"(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nThe updated IOMMUFD uAPI introduces the ability for userspace to request\na specific hardware info data type via IOMMU_GET_HW_INFO. Update\niommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE\nwhen a non-zero type is supplied, and adjust all callers to pass a type\nvalue explicitly initialised to zero (IOMMU_HW_INFO_TYPE_DEFAULT) when\nno specific type is requested.\n\nSigned-off-by: Nicolin Chen \nReviewed-by: Eric Auger \nSigned-off-by: Shameer Kolothum \n---\n backends/iommufd.c | 7 +++++++\n hw/arm/smmuv3-accel.c | 2 +-\n hw/vfio/iommufd.c | 4 ++--\n 3 files changed, 10 insertions(+), 3 deletions(-)","diff":"diff --git a/backends/iommufd.c b/backends/iommufd.c\nindex 52cb060454..20d4186f29 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -397,16 +397,23 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be,\n return true;\n }\n \n+/*\n+ * @type can carry a desired HW info type defined in the uapi headers. If caller\n+ * doesn't have one, indicating it wants the default type, then @type should be\n+ * zeroed (i.e. IOMMU_HW_INFO_TYPE_DEFAULT).\n+ */\n bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid,\n uint32_t *type, void *data, uint32_t len,\n uint64_t *caps, uint8_t *max_pasid_log2,\n Error **errp)\n {\n struct iommu_hw_info info = {\n+ .flags = (*type) ? IOMMU_HW_INFO_FLAG_INPUT_TYPE : 0,\n .size = sizeof(info),\n .dev_id = devid,\n .data_len = len,\n .data_uptr = (uintptr_t)data,\n+ .in_data_type = *type,\n };\n \n if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) {\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 48f8017262..d68d4141a0 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -172,7 +172,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n {\n struct iommu_hw_info_arm_smmuv3 info;\n- uint32_t data_type;\n+ uint32_t data_type = IOMMU_HW_INFO_TYPE_DEFAULT;\n uint64_t caps;\n \n if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data_type,\ndiff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c\nindex 3e33dfbb35..4043111667 100644\n--- a/hw/vfio/iommufd.c\n+++ b/hw/vfio/iommufd.c\n@@ -352,7 +352,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev,\n ERRP_GUARD();\n IOMMUFDBackend *iommufd = vbasedev->iommufd;\n VFIOContainer *bcontainer = VFIO_IOMMU(container);\n- uint32_t type, flags = 0;\n+ uint32_t type = IOMMU_HW_INFO_TYPE_DEFAULT, flags = 0;\n uint64_t hw_caps;\n VendorCaps caps;\n VFIOIOASHwpt *hwpt;\n@@ -941,7 +941,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *hiod, void *opaque,\n HostIOMMUDeviceIOMMUFD *idev;\n HostIOMMUDeviceCaps *caps = &hiod->caps;\n VendorCaps *vendor_caps = &caps->vendor_caps;\n- enum iommu_hw_info_type type;\n+ uint32_t type = IOMMU_HW_INFO_TYPE_DEFAULT;\n uint8_t max_pasid_log2;\n uint64_t hw_caps;\n \n","prefixes":["v4","01/31"]}