{"id":2223458,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223458/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-23-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-23-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:43","name":"[v4,22/31] hw/arm/tegra241-cmdqv: Map VINTF page0 into guest MMIO space","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dd103541ceebf5f10d39b1fd4afcac42b9b5728e","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-23-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223458/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223458/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=JHWKaeTq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3D.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR12MB7341","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nOnce a VCMDQ is allocated, map the mmap'd vintf_page0 region directly\ninto the guest-visible MMIO space at offset 0x30000 as a RAM-backed\nMemoryRegion. This eliminates QEMU trapping for hot-path CONS/PROD\nindex updates.\n\nAfter this patch, the two VCMDQ apertures use different access paths:\nthe direct aperture (0x10000) remains QEMU-trapped and writes via\nvintf_ptr, while the VI aperture (0x30000) is a direct guest RAM\nmapping. Both paths write to the same underlying vintf_page0 memory,\nso no synchronisation between the apertures is needed.\n\nThe mapping is installed lazily on first successful VCMDQ hardware\nqueue allocation and removed when CMDQV or VINTF is disabled.\n\nSigned-off-by: Nicolin Chen \nCo-developed-by: Shameer Kolothum \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.h | 1 +\n hw/arm/tegra241-cmdqv.c | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 38 insertions(+)","diff":"diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 039d86374f..2befa6205e 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -46,6 +46,7 @@ typedef struct Tegra241CMDQV {\n IOMMUFDVeventq *veventq;\n IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ];\n void *vintf_page0;\n+ MemoryRegion *mr_vintf_page0;\n \n /* Register Cache */\n uint32_t config;\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex eb619e1134..bf989dd51f 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -15,6 +15,40 @@\n #include \"tegra241-cmdqv.h\"\n #include \"trace.h\"\n \n+static void tegra241_cmdqv_guest_unmap_vintf_page0(Tegra241CMDQV *cmdqv)\n+{\n+ if (!cmdqv->mr_vintf_page0) {\n+ return;\n+ }\n+\n+ memory_region_del_subregion(&cmdqv->mmio_cmdqv, cmdqv->mr_vintf_page0);\n+ object_unparent(OBJECT(cmdqv->mr_vintf_page0));\n+ g_free(cmdqv->mr_vintf_page0);\n+ cmdqv->mr_vintf_page0 = NULL;\n+}\n+\n+static void tegra241_cmdqv_guest_map_vintf_page0(Tegra241CMDQV *cmdqv)\n+{\n+ char *name;\n+\n+ if (cmdqv->mr_vintf_page0) {\n+ return;\n+ }\n+\n+ name = g_strdup_printf(\"%s vintf-page0\",\n+ memory_region_name(&cmdqv->mmio_cmdqv));\n+ cmdqv->mr_vintf_page0 = g_malloc0(sizeof(*cmdqv->mr_vintf_page0));\n+ memory_region_init_ram_device_ptr(cmdqv->mr_vintf_page0,\n+ memory_region_owner(&cmdqv->mmio_cmdqv),\n+ name, VINTF_PAGE_SIZE,\n+ cmdqv->vintf_page0);\n+ cmdqv->mr_vintf_page0->ram_device_skip_iommu_map = true;\n+ memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv,\n+ CMDQV_VINTF_PAGE0_BASE,\n+ cmdqv->mr_vintf_page0, 1);\n+ g_free(name);\n+}\n+\n static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index)\n {\n IOMMUFDViommu *viommu = cmdqv->s_accel->viommu;\n@@ -72,6 +106,7 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index,\n hw_queue->viommu = viommu;\n cmdqv->vcmdq[index] = hw_queue;\n \n+ tegra241_cmdqv_guest_map_vintf_page0(cmdqv);\n return true;\n }\n \n@@ -312,6 +347,7 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv,\n cmdqv->vintf_status |= R_VINTF0_STATUS_ENABLE_OK_MASK;\n }\n } else {\n+ tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv);\n tegra241_cmdqv_free_all_vcmdq(cmdqv);\n tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp);\n cmdqv->vintf_status &= ~R_VINTF0_STATUS_ENABLE_OK_MASK;\n@@ -438,6 +474,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n if (value & R_CONFIG_CMDQV_EN_MASK) {\n cmdqv->status |= R_STATUS_CMDQV_ENABLED_MASK;\n } else {\n+ tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv);\n tegra241_cmdqv_free_all_vcmdq(cmdqv);\n cmdqv->status &= ~R_STATUS_CMDQV_ENABLED_MASK;\n }\n","prefixes":["v4","22/31"]}