{"id":2223453,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223453/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-21-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-21-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:41","name":"[v4,20/31] hw/arm/tegra241-cmdqv: Use mmap'd VINTF page0 as VCMDQ backing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fea8322332d1059c6a121433507e72760b42ff09","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-21-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223453/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223453/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=LLQ6/SZ9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C","permerror client-ip=2a01:111:f403:c105::5;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH5PR02CU005.outbound.protection.outlook.com"],"From":"Shameer Kolothum ","To":", ","CC":", , ,\n , , ,\n , , ,\n , ,\n , , ","Subject":"[PATCH v4 20/31] hw/arm/tegra241-cmdqv: Use mmap'd VINTF page0 as\n VCMDQ backing","Date":"Wed, 15 Apr 2026 11:55:41 +0100","Message-ID":"<20260415105552.622421-21-skolothumtho@nvidia.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260415105552.622421-1-skolothumtho@nvidia.com>","References":"<20260415105552.622421-1-skolothumtho@nvidia.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.126.230.37]","X-ClientProxiedBy":"rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"CY4PEPF0000EE3D:EE_|DS0PR12MB7581:EE_","X-MS-Office365-Filtering-Correlation-Id":"e48247ac-a224-44c1-372f-08de9adddf37","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|36860700016|82310400026|1800799024|376014|22082099003|56012099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n TtqaLwwEu1J8tnQX4+Pn8tj2d8ecBaHfQ5phA/vJZS1icT2vAGEftCQ6LgCe+mLZ0zwqa0vwjHBJeopwbpzwI/MaNRA9YWDWnXGi9hG1EsNARZW8ELAUYxhysU+qxVRqE6wWnXO+oVDt5rQVUGwQN+rKsOKPwLeMy2Lcg0kqpayOuYUG6EQlbb0fB34jVlWS6+1UbRnHV44K0FlFuVwx5LNQUV7ngKyKFyX0HHhsZmtuRTL1E7pUVXFl5tasLUP/Rjx1z9IPn+o16p14JynzLiEeZY8ShgM8nwFCt2yIiDKScEB2lPxX6fX8Svg44iMCN9grMiab/j6SUyhaJm6zkaL8zfVnPi0l95X7NGN3STyB5513Tk3K4lqkXWgH6lb76q6pBYmknrErAinhvAuM2XBWbRVZ7R3eTWKIEu/OdC+j95ZIdb4I3hriwgSQoOW4WKRq6elS++Ofi+kCHu0aScrpOEZNpgwcLusYIsQjTCxcOntyRteL0/B/PhohTDDq8EqxSQNYDuYTI6BsSD0FoM+xTSeJrDWpFw/ddpVzQnGpfp4jHdCJ9dFumRhqoEweWQ6p8XgEfrxyV324uUyWx5Cgx8UptD2Hy2Nl09+SvPr6qNaIoFTGEsCkIyfEC6TIZToG6uDMkQaj451bYbXmJFj2QnBVPOAMr3Yeygu54WeAz/dgOtGQNpXMbDDvqHwj82gE0lo9dAajSses1qQskuCgfx+Lb7A+PO4YoeLmnYfSZi9mUP1x1Lc/hIEo3ShwKoFG3ggjB68U/Tu9cDNqzQ==","X-Forefront-Antispam-Report":"CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3D.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS0PR12MB7581","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Introduce tegra241_cmdqv_vintf_ptr() to route VCMDQ register accesses\nthrough the mmap'd VINTF page0 backing once a hardware queue has been\nallocated.\n\nThere are two QEMU trapped MMIO apertures for VCMDQ registers:\n\n - Direct VCMDQ aperture (offset 0x10000)\n - VINTF Page0 (offset 0x30000)\n\nThese are hardware aliases: they address the same underlying registers.\nA subsequent patch maps the VINTF aperture as a guest-direct RAM region;\nin this patch both remain QEMU-trapped.\n\nVCMDQ register accesses operate in one of two mutually exclusive modes,\ndepending on whether a hardware queue (IOMMU_HW_QUEUE_ALLOC) has been\nallocated for the VCMDQ:\n\nPre-alloc: vintf_ptr is NULL. Both apertures use QEMU's register\ncache. Hardware is not yet engaged;\n\nPost-alloc: vintf_ptr is valid. Both QEMU trapped apertures access\nregisters directly via the mmap'd vintf_page0 pointer, bypassing\nthe cache. Hardware is the single source of truth.\n\nThe pre-to-post-alloc transition is triggered by the BASE register write\nthat initiates IOMMU_HW_QUEUE_ALLOC. No cache-to-hardware synchronisation\nis needed at transition time. The hardware mandated init sequence requires\nBASE to be written first; PROD_INDX, CONS_INDX and CONFIG.CMDQ_EN are\nprogrammed only after BASE and are therefore always post-alloc.\n\nAny pre-alloc writes to those registers update only the register cache,\nwhich is discarded at the transition.\n\nCMDQV acceleration only becomes active once the guest enables VINTF and\nprograms the VCMDQ BASE register. Until then, all VCMDQ accesses are\nserved from the emulated register cache with no real hardware command\nprocessing. This matches the CMDQV hardware specification: if the logical\nCMDQ index does not map to any allocated Virtual CMDQ, \"the access is\ndropped with no Fault/Interrupt\".\n\nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.c | 48 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 47 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex b5f2f74cf2..eb619e1134 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -75,17 +75,45 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index,\n return true;\n }\n \n+static inline uint32_t *tegra241_cmdqv_vintf_ptr(Tegra241CMDQV *cmdqv,\n+ int index, hwaddr offset0)\n+{\n+ if (!cmdqv->vcmdq[index] || !cmdqv->vintf_page0) {\n+ return NULL;\n+ }\n+ return (uint32_t *)(cmdqv->vintf_page0 +\n+ (index * CMDQV_VCMDQ_STRIDE) +\n+ (offset0 - CMDQV_VCMDQ_PAGE0_BASE));\n+}\n+\n /*\n * Read a VCMDQ register using VCMDQ0_* offsets.\n *\n * The caller normalizes the MMIO offset such that @offset0 always refers\n * to a VCMDQ0_* register, while @index selects the VCMDQ instance.\n *\n- * All VCMDQ accesses return cached registers.\n+ * If the VCMDQ is allocated and VINTF page0 is mmap'd, read directly\n+ * from the VINTF page0 backing. Otherwise, fall back to cached state.\n */\n static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n int index)\n {\n+ uint32_t *ptr = tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0);\n+\n+ if (ptr) {\n+ switch (offset0) {\n+ case A_VCMDQ0_CONS_INDX:\n+ case A_VCMDQ0_PROD_INDX:\n+ case A_VCMDQ0_CONFIG:\n+ case A_VCMDQ0_STATUS:\n+ case A_VCMDQ0_GERROR:\n+ case A_VCMDQ0_GERRORN:\n+ return *ptr;\n+ default:\n+ break;\n+ }\n+ }\n+\n switch (offset0) {\n case A_VCMDQ0_CONS_INDX:\n return cmdqv->vcmdq_cons_indx[index];\n@@ -120,11 +148,29 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n *\n * The caller normalizes the MMIO offset such that @offset0 always refers\n * to a VCMDQ0_* register, while @index selects the VCMDQ instance.\n+ *\n+ * If the VCMDQ is allocated and VINTF page0 is mmap'd, write directly\n+ * to the VINTF page0 backing. Otherwise, update cached state.\n */\n static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n int index, uint64_t value,\n unsigned size, Error **errp)\n {\n+ uint32_t *ptr = tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0);\n+\n+ if (ptr) {\n+ switch (offset0) {\n+ case A_VCMDQ0_CONS_INDX:\n+ case A_VCMDQ0_PROD_INDX:\n+ case A_VCMDQ0_CONFIG:\n+ case A_VCMDQ0_GERRORN:\n+ *ptr = (uint32_t)value;\n+ return;\n+ default:\n+ break;\n+ }\n+ }\n+\n switch (offset0) {\n case A_VCMDQ0_CONS_INDX:\n cmdqv->vcmdq_cons_indx[index] = (uint32_t)value;\n","prefixes":["v4","20/31"]}