{"id":2223451,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223451/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-26-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-26-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:46","name":"[v4,25/31] hw/arm/tegra241-cmdqv: Add reset handler","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5b382fa065c0384cffc752e5e670dbca5fc2d844","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-26-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223451/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223451/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=gupRT6dC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3E.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SJ2PR12MB8783","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nIntroduce a reset handler for the Tegra241 CMDQV and initialize its\nregister state.\n\nSigned-off-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.h | 2 ++\n hw/arm/tegra241-cmdqv.c | 50 +++++++++++++++++++++++++++++++++++++++++\n hw/arm/trace-events | 1 +\n 3 files changed, 53 insertions(+)","diff":"diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 2befa6205e..b2a444daef 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -79,6 +79,8 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8)\n FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8)\n FIELD(CONFIG, CONS_DRAM_EN, 20, 1)\n \n+#define V_CONFIG_RESET 0x00020403\n+\n REG32(PARAM, 0x4)\n FIELD(PARAM, CMDQV_VER, 0, 4)\n FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4)\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 9c2fc02b92..af68add2f0 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -8,6 +8,7 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"qemu/error-report.h\"\n #include \"qemu/log.h\"\n \n #include \"hw/arm/smmuv3.h\"\n@@ -645,8 +646,57 @@ free_viommu:\n return false;\n }\n \n+static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv)\n+{\n+ int i;\n+\n+ cmdqv->config = V_CONFIG_RESET;\n+ cmdqv->param = FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER);\n+ cmdqv->param = FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2,\n+ CMDQV_NUM_CMDQ_LOG2);\n+ cmdqv->param = FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VI_LOG2,\n+ CMDQV_NUM_SID_PER_VI_LOG2);\n+ trace_tegra241_cmdqv_init_regs(cmdqv->param);\n+ cmdqv->status = R_STATUS_CMDQV_ENABLED_MASK;\n+ for (i = 0; i < 2; i++) {\n+ cmdqv->vi_err_map[i] = 0;\n+ cmdqv->vi_int_mask[i] = 0;\n+ cmdqv->cmdq_err_map[i] = 0;\n+ }\n+ cmdqv->cmdq_err_map[2] = 0;\n+ cmdqv->cmdq_err_map[3] = 0;\n+ cmdqv->vintf_config = 0;\n+ cmdqv->vintf_status = 0;\n+ for (i = 0; i < 4; i++) {\n+ cmdqv->vintf_cmdq_err_map[i] = 0;\n+ }\n+ for (i = 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) {\n+ cmdqv->cmdq_alloc_map[i] = 0;\n+ cmdqv->vcmdq_cons_indx[i] = 0;\n+ cmdqv->vcmdq_prod_indx[i] = 0;\n+ cmdqv->vcmdq_config[i] = 0;\n+ cmdqv->vcmdq_status[i] = 0;\n+ cmdqv->vcmdq_gerror[i] = 0;\n+ cmdqv->vcmdq_gerrorn[i] = 0;\n+ cmdqv->vcmdq_base[i] = 0;\n+ cmdqv->vcmdq_cons_indx_base[i] = 0;\n+ }\n+}\n+\n static void tegra241_cmdqv_reset(SMMUv3State *s)\n {\n+ SMMUv3AccelState *accel = s->s_accel;\n+ Tegra241CMDQV *cmdqv = accel->cmdqv;\n+\n+ if (!cmdqv) {\n+ return;\n+ }\n+\n+ tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv);\n+ tegra241_cmdqv_munmap_vintf_page0(cmdqv, NULL);\n+ tegra241_cmdqv_free_all_vcmdq(cmdqv);\n+\n+ tegra241_cmdqv_init_regs(s, cmdqv);\n }\n \n static const MemoryRegionOps mmio_cmdqv_ops = {\ndiff --git a/hw/arm/trace-events b/hw/arm/trace-events\nindex fd6441bfa7..6f602b9eda 100644\n--- a/hw/arm/trace-events\n+++ b/hw/arm/trace-events\n@@ -76,6 +76,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) \"vS\n tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) \"offset: 0x%\"PRIx64\" val: 0x%\"PRIx64\" size: 0x%x\"\n tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) \"offset: 0x%\"PRIx64\" val: 0x%\"PRIx64\" size: 0x%x\"\n tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32_t map0) \"hw irq received. error (hex) maps: %04X:%04X:%04X:%04X\"\n+tegra241_cmdqv_init_regs(uint32_t param) \"hw info received. param: 0x%04X\"\n \n # strongarm.c\n strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) \"%s speed=%d parity=%c data=%d stop=%d\"\n","prefixes":["v4","25/31"]}