{"id":2223450,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223450/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-20-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-20-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:40","name":"[v4,19/31] hw/arm/tegra241-cmdqv: Allocate HW VCMDQs on base register programming","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"67c1d647217bdea0c89a6865d77439798cc1263c","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-20-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223450/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223450/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=EK2MWn2j;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BL02EPF00021F6B.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PH8PR12MB6843","X-Spam_score_int":"-25","X-Spam_score":"-2.6","X-Spam_bar":"--","X-Spam_report":"(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nAdd support for allocating IOMMUFD hardware queues when the guest\nprograms the VCMDQ BASE registers.\n\nVCMDQ_EN is part of the VCMDQ_CONFIG register, which is accessed\nthrough the VINTF Page0 region. A subsequent patch maps this region\ndirectly into the guest address space, so QEMU does not trap writes\nto VCMDQ_CONFIG.\n\nSince VCMDQ_EN writes are not trapped, QEMU cannot allocate the\nhardware queue based on that bit. Instead, allocate the IOMMUFD\nhardware queue when the guest writes a VCMDQ BASE register with a\nvalid RAM-backed address and when CMDQV and VINTF are enabled.\n\nIf a hardware queue was previously allocated for the same VCMDQ,\nfree it before reallocation.\n\nWrites with invalid addresses are ignored.\n\nAll allocated VCMDQs are freed when CMDQV or VINTF is disabled.\n\nSigned-off-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.h | 11 +++++++\n hw/arm/tegra241-cmdqv.c | 70 +++++++++++++++++++++++++++++++++++++++--\n 2 files changed, 78 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 88572ad939..039d86374f 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -44,6 +44,7 @@ typedef struct Tegra241CMDQV {\n MemoryRegion mmio_cmdqv;\n qemu_irq irq;\n IOMMUFDVeventq *veventq;\n+ IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ];\n void *vintf_page0;\n \n /* Register Cache */\n@@ -348,6 +349,16 @@ A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(1)\n A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0)\n A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(1)\n \n+static inline bool tegra241_cmdq_enabled(Tegra241CMDQV *cmdqv)\n+{\n+ return cmdqv->status & R_STATUS_CMDQV_ENABLED_MASK;\n+}\n+\n+static inline bool tegra241_vintf_enabled(Tegra241CMDQV *cmdqv)\n+{\n+ return cmdqv->vintf_status & R_VINTF0_STATUS_ENABLE_OK_MASK;\n+}\n+\n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n \n #endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex cdd941cec9..b5f2f74cf2 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -15,6 +15,66 @@\n #include \"tegra241-cmdqv.h\"\n #include \"trace.h\"\n \n+static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index)\n+{\n+ IOMMUFDViommu *viommu = cmdqv->s_accel->viommu;\n+ IOMMUFDHWqueue *vcmdq = cmdqv->vcmdq[index];\n+\n+ if (!vcmdq) {\n+ return;\n+ }\n+ iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id);\n+ g_free(vcmdq);\n+ cmdqv->vcmdq[index] = NULL;\n+}\n+\n+static void tegra241_cmdqv_free_all_vcmdq(Tegra241CMDQV *cmdqv)\n+{\n+ /* Free in reverse order to avoid \"resource busy\" error */\n+ for (int i = (TEGRA241_CMDQV_MAX_CMDQ - 1); i >= 0; i--) {\n+ tegra241_cmdqv_free_vcmdq(cmdqv, i);\n+ }\n+}\n+\n+static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index,\n+ Error **errp)\n+{\n+ SMMUv3AccelState *accel = cmdqv->s_accel;\n+ uint64_t base_mask = (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK |\n+ (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32;\n+ uint64_t addr = cmdqv->vcmdq_base[index] & base_mask;\n+ uint64_t log2 = cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_MASK;\n+ uint64_t size = 1ULL << (log2 + 4);\n+ IOMMUFDViommu *viommu = accel->viommu;\n+ IOMMUFDHWqueue *hw_queue;\n+ uint32_t hw_queue_id;\n+\n+ /* Ignore any invalid address. This may come as part of reset etc. */\n+ if (!address_space_is_ram(&address_space_memory, addr) ||\n+ !address_space_is_ram(&address_space_memory, addr + size - 1)) {\n+ return true;\n+ }\n+\n+ if (!tegra241_cmdq_enabled(cmdqv) || !tegra241_vintf_enabled(cmdqv)) {\n+ return true;\n+ }\n+\n+ tegra241_cmdqv_free_vcmdq(cmdqv, index);\n+\n+ if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id,\n+ IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV,\n+ index, addr, size, &hw_queue_id,\n+ errp)) {\n+ return false;\n+ }\n+ hw_queue = g_new(IOMMUFDHWqueue, 1);\n+ hw_queue->hw_queue_id = hw_queue_id;\n+ hw_queue->viommu = viommu;\n+ cmdqv->vcmdq[index] = hw_queue;\n+\n+ return true;\n+}\n+\n /*\n * Read a VCMDQ register using VCMDQ0_* offsets.\n *\n@@ -63,7 +123,7 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n */\n static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n int index, uint64_t value,\n- unsigned size)\n+ unsigned size, Error **errp)\n {\n switch (offset0) {\n case A_VCMDQ0_CONS_INDX:\n@@ -91,11 +151,13 @@ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) |\n (value & 0xffffffffULL);\n }\n+ tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp);\n return;\n case A_VCMDQ0_BASE_H:\n cmdqv->vcmdq_base[index] =\n (cmdqv->vcmdq_base[index] & 0xffffffffULL) |\n ((uint64_t)value << 32);\n+ tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp);\n return;\n case A_VCMDQ0_CONS_INDX_BASE_DRAM_L:\n if (size == 8) {\n@@ -204,6 +266,7 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv,\n cmdqv->vintf_status |= R_VINTF0_STATUS_ENABLE_OK_MASK;\n }\n } else {\n+ tegra241_cmdqv_free_all_vcmdq(cmdqv);\n tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp);\n cmdqv->vintf_status &= ~R_VINTF0_STATUS_ENABLE_OK_MASK;\n }\n@@ -329,6 +392,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n if (value & R_CONFIG_CMDQV_EN_MASK) {\n cmdqv->status |= R_STATUS_CMDQV_ENABLED_MASK;\n } else {\n+ tegra241_cmdqv_free_all_vcmdq(cmdqv);\n cmdqv->status &= ~R_STATUS_CMDQV_ENABLED_MASK;\n }\n break;\n@@ -363,7 +427,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n */\n index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE;\n tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE,\n- index, value, size);\n+ index, value, size, &local_err);\n break;\n case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */\n@@ -373,7 +437,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n /* Same decode logic as VCMDQ Page0 case above */\n index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE;\n tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE,\n- index, value, size);\n+ index, value, size, &local_err);\n break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n","prefixes":["v4","19/31"]}