{"id":2223442,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223442/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-12-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-12-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:32","name":"[v4,11/31] hw/arm/tegra241-cmdqv: Implement CMDQV init","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d66aa3f783c952206cc056426b21d8e892501d18","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-12-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223442/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223442/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=o7MP/bJE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3F.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR12MB8164","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nTegra241 CMDQV extends SMMUv3 with support for virtual command queues\n(VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split\ninto 64KB pages:\n\n0x00000 (CMDQ-V Config page)\n0x10000 (CMDQ-V CMDQ Page0)\n0x20000 (CMDQ-V CMDQ Page1)\n0x30000 (Virtual Interface Page0)\n0x40000 (Virtual Interface Page1)\n\nThis patch wires up the Tegra241 CMDQV init callback and allocates\nvendor-specific CMDQV state. The state pointer is stored in\nSMMUv3AccelState for use by subsequent CMDQV operations.\n\nThe CMDQV MMIO region and a dedicated IRQ line are registered with the\nSMMUv3 device. The MMIO read/write handlers are currently stubs and will\nbe implemented in later patches.\n\nThe CMDQV interrupt is edge-triggered and indicates VCMDQ or VINTF\nerror conditions. This patch only registers the IRQ line. Interrupt\ngeneration and propagation to the guest will be added in a subsequent\npatch.\n\nSigned-off-by: Nicolin Chen \nReviewed-by: Eric Auger \nCo-developed-by: Shameer Kolothum \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/smmuv3-accel.h | 1 +\n hw/arm/tegra241-cmdqv.h | 18 ++++++++++++++++++\n hw/arm/tegra241-cmdqv.c | 30 ++++++++++++++++++++++++++++--\n 3 files changed, 47 insertions(+), 2 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex 86301afcb4..28bceca061 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -45,6 +45,7 @@ typedef struct SMMUv3AccelState {\n bool auto_mode;\n bool auto_finalised;\n const SMMUv3AccelCmdqvOps *cmdqv_ops;\n+ void *cmdqv; /* vendor specific CMDQV state */\n } SMMUv3AccelState;\n \n typedef struct SMMUS1Hwpt {\ndiff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex c1866084f8..2a34a4b6b4 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -14,6 +14,24 @@\n #define CMDQV_NUM_CMDQ_LOG2 1\n #define CMDQV_NUM_SID_PER_VI_LOG2 4\n \n+/*\n+ * Tegra241 CMDQV MMIO layout (64KB pages)\n+ *\n+ * 0x00000 (CMDQ-V Config page)\n+ * 0x10000 (CMDQ-V CMDQ Page0)\n+ * 0x20000 (CMDQ-V CMDQ Page1)\n+ * 0x30000 (Virtual Interface Page0)\n+ * 0x40000 (Virtual Interface Page1)\n+ */\n+#define TEGRA241_CMDQV_IO_LEN 0x50000\n+\n+typedef struct Tegra241CMDQV {\n+ struct iommu_viommu_tegra241_cmdqv cmdqv_data;\n+ SMMUv3AccelState *s_accel;\n+ MemoryRegion mmio_cmdqv;\n+ qemu_irq irq;\n+} Tegra241CMDQV;\n+\n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n \n #endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 3a19a1af56..ccd3c6d275 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -13,6 +13,16 @@\n #include \"smmuv3-accel.h\"\n #include \"tegra241-cmdqv.h\"\n \n+static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned size)\n+{\n+ return 0;\n+}\n+\n+static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t value,\n+ unsigned size)\n+{\n+}\n+\n static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n {\n }\n@@ -29,10 +39,26 @@ static void tegra241_cmdqv_reset(SMMUv3State *s)\n {\n }\n \n+static const MemoryRegionOps mmio_cmdqv_ops = {\n+ .read = tegra241_cmdqv_read,\n+ .write = tegra241_cmdqv_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+};\n+\n static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp)\n {\n- error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n- return false;\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(OBJECT(s));\n+ SMMUv3AccelState *accel = s->s_accel;\n+ Tegra241CMDQV *cmdqv;\n+\n+ cmdqv = g_new0(Tegra241CMDQV, 1);\n+ memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, cmdqv,\n+ \"tegra241-cmdqv\", TEGRA241_CMDQV_IO_LEN);\n+ sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv);\n+ sysbus_init_irq(sbd, &cmdqv->irq);\n+ cmdqv->s_accel = accel;\n+ accel->cmdqv = cmdqv;\n+ return true;\n }\n \n static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n","prefixes":["v4","11/31"]}