{"id":2223440,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223440/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-17-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-17-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:37","name":"[v4,16/31] hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4299c38b8d51c839bb65e7c606e2b6412f395883","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-17-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223440/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223440/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=T2ofGS+Z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE3B.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"LV2PR12MB5941","X-Spam_score_int":"-25","X-Spam_score":"-2.6","X-Spam_bar":"--","X-Spam_report":"(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nThis is the write side counterpart of the VCMDQ read emulation. Add write\nhandling for both CMDQV_CMDQ_BASE and CMDQV_VI_CMDQ_BASE apertures using\nthe same index decoding and VINTF-to-VCMDQ translation logic as the read\npath.\n\nVINTF aperture writes are translated to their CMDQV_CMDQ_BASE equivalent\nand update the same cached state. Page1 registers (BASE, CONS_INDX_BASE)\nalways update the cache. Once IOMMU_HW_QUEUE_ALLOC and viommu_mmap are\nwired up in a subsequent patch, Page0 register writes will be forwarded\nto the hardware-backed mmap'd page.\n\nSigned-off-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.c | 99 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 99 insertions(+)","diff":"diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 35e6f0bbd6..d4ba2ada92 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -55,6 +55,70 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n }\n }\n \n+/*\n+ * Write a VCMDQ register using VCMDQ0_* offsets.\n+ *\n+ * The caller normalizes the MMIO offset such that @offset0 always refers\n+ * to a VCMDQ0_* register, while @index selects the VCMDQ instance.\n+ */\n+static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n+ int index, uint64_t value,\n+ unsigned size)\n+{\n+ switch (offset0) {\n+ case A_VCMDQ0_CONS_INDX:\n+ cmdqv->vcmdq_cons_indx[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_PROD_INDX:\n+ cmdqv->vcmdq_prod_indx[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_CONFIG:\n+ if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) {\n+ cmdqv->vcmdq_status[index] |= R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK;\n+ } else {\n+ cmdqv->vcmdq_status[index] &= ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK;\n+ }\n+ cmdqv->vcmdq_config[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_GERRORN:\n+ cmdqv->vcmdq_gerrorn[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_BASE_L:\n+ if (size == 8) {\n+ cmdqv->vcmdq_base[index] = value;\n+ } else {\n+ cmdqv->vcmdq_base[index] =\n+ (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) |\n+ (value & 0xffffffffULL);\n+ }\n+ return;\n+ case A_VCMDQ0_BASE_H:\n+ cmdqv->vcmdq_base[index] =\n+ (cmdqv->vcmdq_base[index] & 0xffffffffULL) |\n+ ((uint64_t)value << 32);\n+ return;\n+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_L:\n+ if (size == 8) {\n+ cmdqv->vcmdq_cons_indx_base[index] = value;\n+ } else {\n+ cmdqv->vcmdq_cons_indx_base[index] =\n+ (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffff00000000ULL) |\n+ (value & 0xffffffffULL);\n+ }\n+ return;\n+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_H:\n+ cmdqv->vcmdq_cons_indx_base[index] =\n+ (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffffULL) |\n+ ((uint64_t)value << 32);\n+ return;\n+ default:\n+ qemu_log_mask(LOG_UNIMP,\n+ \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset0);\n+ return;\n+ }\n+}\n+\n static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,\n hwaddr offset)\n {\n@@ -212,6 +276,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n uint64_t value, unsigned size)\n {\n Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;\n+ int index;\n \n if (offset >= TEGRA241_CMDQV_IO_LEN) {\n qemu_log_mask(LOG_UNIMP,\n@@ -238,6 +303,40 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n tegra241_cmdqv_config_vintf_write(cmdqv, offset, value);\n break;\n+ case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN:\n+ /*\n+ * VINTF Page0 registers have the same per-VCMDQ layout as the\n+ * VCMDQ Page0 registers. Translate the VINTF aperture offset to the\n+ * equivalent VCMDQ aperture offset, then fall through to reuse the\n+ * common VCMDQ decoding logic below.\n+ */\n+ offset -= CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE;\n+ QEMU_FALLTHROUGH;\n+ case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN:\n+ /*\n+ * Decode a per-VCMDQ register access.\n+ *\n+ * The hardware supports up to 128 identical VCMDQ instances; we\n+ * currently expose TEGRA241_CMDQV_MAX_CMDQ (= 2). Each VCMDQ\n+ * occupies a CMDQV_VCMDQ_STRIDE-byte window within the page.\n+ *\n+ * Extract the VCMDQ index and normalize to the VCMDQ0_* register\n+ * offset. A single helper services all instances via @index.\n+ */\n+ index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE;\n+ tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE,\n+ index, value, size);\n+ break;\n+ case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n+ /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */\n+ offset -= CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE;\n+ QEMU_FALLTHROUGH;\n+ case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n+ /* Same decode logic as VCMDQ Page0 case above */\n+ index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE;\n+ tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE,\n+ index, value, size);\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n __func__, offset);\n","prefixes":["v4","16/31"]}