{"id":2223437,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223437/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-10-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-10-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:30","name":"[v4,09/31] hw/arm/virt: Use stored SMMUv3 device list for IORT build","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"598edf76c69bd626527ed210a61c0bc2f660558d","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-10-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223437/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223437/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=QqztvOdp;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BL02EPF00021F69.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SJ2PR12MB8783","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Introduce a GPtrArray in VirtMachineState to track all SMMUv3 devices\ncreated on the virt machine, and use it when building the IORT table\ninstead of relying on object_child_foreach_recursive() walks of the\nobject tree.\n\nThis avoids recursive object traversal and provides a foundation for\nsubsequent patches that need direct access to SMMUv3 instances for\nCMDQV-related handling.\n\nNo functional change. No bios-tables qtest failures observed.\n\nReviewed-by: Eric Auger \nSigned-off-by: Shameer Kolothum \n---\n include/hw/arm/virt.h | 1 +\n hw/arm/virt-acpi-build.c | 70 ++++++++++++++++++----------------------\n hw/arm/virt.c | 3 ++\n 3 files changed, 35 insertions(+), 39 deletions(-)","diff":"diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 5fcbd1c76f..a840a97de8 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -187,6 +187,7 @@ struct VirtMachineState {\n MemoryRegion *sysmem;\n MemoryRegion *secure_sysmem;\n bool pci_preserve_config;\n+ GPtrArray *smmuv3_devices;\n };\n \n #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)\ndiff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 591cfc993c..521443de87 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -385,49 +385,41 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b)\n return map_a->input_base - map_b->input_base;\n }\n \n-static int iort_smmuv3_devices(Object *obj, void *opaque)\n-{\n- VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());\n- AcpiIortSMMUv3Dev sdev = {0};\n- GArray *sdev_blob = opaque;\n- AcpiIortIdMapping idmap;\n- PlatformBusDevice *pbus;\n- int min_bus, max_bus;\n- SysBusDevice *sbdev;\n- PCIBus *bus;\n-\n- if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) {\n- return 0;\n- }\n-\n- bus = PCI_BUS(object_property_get_link(obj, \"primary-bus\", &error_abort));\n- sdev.accel = object_property_get_bool(obj, \"accel\", &error_abort);\n- sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));\n- pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n- sbdev = SYS_BUS_DEVICE(obj);\n- sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);\n- sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;\n- sdev.irq = platform_bus_get_irqn(pbus, sbdev, 0);\n- sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];\n- sdev.irq += ARM_SPI_BASE;\n-\n- pci_bus_range(bus, &min_bus, &max_bus);\n- sdev.rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));\n- idmap.input_base = min_bus << 8,\n- idmap.id_count = (max_bus - min_bus + 1) << 8,\n- g_array_append_val(sdev.rc_smmu_idmaps, idmap);\n- g_array_append_val(sdev_blob, sdev);\n- return 0;\n-}\n-\n /*\n * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and\n * return the total number of idmaps.\n */\n-static int populate_smmuv3_dev(GArray *sdev_blob)\n+static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob)\n {\n- object_child_foreach_recursive(object_get_root(),\n- iort_smmuv3_devices, sdev_blob);\n+ for (int i = 0; i < vms->smmuv3_devices->len; i++) {\n+ Object *obj = OBJECT(g_ptr_array_index(vms->smmuv3_devices, i));\n+ AcpiIortSMMUv3Dev sdev = {0};\n+ AcpiIortIdMapping idmap;\n+ PlatformBusDevice *pbus;\n+ int min_bus, max_bus;\n+ SysBusDevice *sbdev;\n+ PCIBus *bus;\n+\n+ bus = PCI_BUS(object_property_get_link(obj, \"primary-bus\",\n+ &error_abort));\n+ sdev.accel = object_property_get_bool(obj, \"accel\", &error_abort);\n+ sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));\n+ pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n+ sbdev = SYS_BUS_DEVICE(obj);\n+ sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);\n+ sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;\n+ sdev.irq = platform_bus_get_irqn(pbus, sbdev, 0);\n+ sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];\n+ sdev.irq += ARM_SPI_BASE;\n+\n+ pci_bus_range(bus, &min_bus, &max_bus);\n+ sdev.rc_smmu_idmaps = g_array_new(false, true,\n+ sizeof(AcpiIortIdMapping));\n+ idmap.input_base = min_bus << 8;\n+ idmap.id_count = (max_bus - min_bus + 1) << 8;\n+ g_array_append_val(sdev.rc_smmu_idmaps, idmap);\n+ g_array_append_val(sdev_blob, sdev);\n+ }\n /* Sort the smmuv3 devices(if any) by smmu idmap input_base */\n g_array_sort(sdev_blob, smmuv3_dev_idmap_compare);\n /*\n@@ -561,7 +553,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n if (vms->legacy_smmuv3_present) {\n rc_smmu_idmaps_len = populate_smmuv3_legacy_dev(smmuv3_devs);\n } else {\n- rc_smmu_idmaps_len = populate_smmuv3_dev(smmuv3_devs);\n+ rc_smmu_idmaps_len = populate_smmuv3_dev(vms, smmuv3_devs);\n }\n \n num_smmus = smmuv3_devs->len;\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ec0d8475ca..68464ceb14 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -3261,6 +3261,7 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,\n }\n \n create_smmuv3_dev_dtb(vms, dev, bus, errp);\n+ g_ptr_array_add(vms->smmuv3_devices, dev);\n }\n }\n \n@@ -3697,6 +3698,8 @@ static void virt_instance_init(Object *obj)\n vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);\n vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);\n cxl_machine_init(obj, &vms->cxl_devices_state);\n+\n+ vms->smmuv3_devices = g_ptr_array_new_with_free_func(NULL);\n }\n \n static const TypeInfo virt_machine_info = {\n","prefixes":["v4","09/31"]}