{"id":2223436,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223436/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-11-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-11-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:31","name":"[v4,10/31] hw/arm/tegra241-cmdqv: Probe host Tegra241 CMDQV support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d56fa84debbcff3ba95740d017aad440bc15e810","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-11-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223436/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223436/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=QNAJ7g4D;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CY4PEPF0000EE39.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CH1PPF84B7B0C96","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use IOMMU_GET_HW_INFO to query host support for Tegra241 CMDQV.\n\nValidate the returned data type, version, and minimum number of vCMDQs and\nSIDs per Tegra241 CMDQ Virtual Interface(VI). Fail the probe if the host\ndoes not meet these requirements.\n\nThe QEMU model supports one Virtual Interface(VI) per VM with 2 vCMDQs and\n16 SIDs per VI, so the probe ensures the host implementation is compatible\nwith these limits.\n\nReviewed-by: Eric Auger \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/tegra241-cmdqv.h | 4 ++++\n hw/arm/tegra241-cmdqv.c | 32 ++++++++++++++++++++++++++++++--\n 2 files changed, 34 insertions(+), 2 deletions(-)","diff":"diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex 07e10e86ee..c1866084f8 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -10,6 +10,10 @@\n #ifndef HW_ARM_TEGRA241_CMDQV_H\n #define HW_ARM_TEGRA241_CMDQV_H\n \n+#define CMDQV_VER 1\n+#define CMDQV_NUM_CMDQ_LOG2 1\n+#define CMDQV_NUM_SID_PER_VI_LOG2 4\n+\n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n \n #endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex ad5a0d4611..3a19a1af56 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -38,8 +38,36 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp)\n static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n {\n- error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n- return false;\n+ uint32_t data_type = IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV;\n+ struct iommu_hw_info_tegra241_cmdqv cmdqv_info;\n+ uint64_t caps;\n+\n+ if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data_type,\n+ &cmdqv_info, sizeof(cmdqv_info), &caps,\n+ NULL, errp)) {\n+ return false;\n+ }\n+ if (data_type != IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) {\n+ error_setg(errp, \"Host CMDQV: unexpected data type %u (expected %u)\",\n+ data_type, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV);\n+ return false;\n+ }\n+ if (cmdqv_info.version != CMDQV_VER) {\n+ error_setg(errp, \"Host CMDQV: unsupported version %u (expected %u)\",\n+ cmdqv_info.version, CMDQV_VER);\n+ return false;\n+ }\n+ if (cmdqv_info.log2vcmdqs < CMDQV_NUM_CMDQ_LOG2) {\n+ error_setg(errp, \"Host CMDQV: insufficient vCMDQs log2=%u (need >= %u)\",\n+ cmdqv_info.log2vcmdqs, CMDQV_NUM_CMDQ_LOG2);\n+ return false;\n+ }\n+ if (cmdqv_info.log2vsids < CMDQV_NUM_SID_PER_VI_LOG2) {\n+ error_setg(errp, \"Host CMDQV: insufficient SIDs log2=%u (need >= %u)\",\n+ cmdqv_info.log2vsids, CMDQV_NUM_SID_PER_VI_LOG2);\n+ return false;\n+ }\n+ return true;\n }\n \n static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops = {\n","prefixes":["v4","10/31"]}