{"id":2223434,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223434/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-3-skolothumtho@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415105552.622421-3-skolothumtho@nvidia.com>","list_archive_url":null,"date":"2026-04-15T10:55:23","name":"[v4,02/31] backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"47b9f2b0a09de822687e4f09f650841e2a293bf6","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.2/people/91580/?format=json","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-3-skolothumtho@nvidia.com/mbox/","series":[{"id":499965,"url":"http://patchwork.ozlabs.org/api/1.2/series/499965/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965","date":"2026-04-15T10:55:21","name":"hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499965/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223434/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223434/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ggv3hm+G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BL02EPF00021F6A.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS0PR12MB7971","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nThe updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data\nbuffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend\niommufd_backend_alloc_viommu() to pass a user pointer and size to the\nkernel.\n\nUpdate the caller accordingly.\n\nSigned-off-by: Nicolin Chen \nReviewed-by: Eric Auger \nSigned-off-by: Shameer Kolothum \n---\n include/system/iommufd.h | 1 +\n backends/iommufd.c | 4 ++++\n hw/arm/smmuv3-accel.c | 4 ++--\n backends/trace-events | 2 +-\n 4 files changed, 8 insertions(+), 3 deletions(-)","diff":"diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex 7062944fe6..e027800c91 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -89,6 +89,7 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,\n Error **errp);\n bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id,\n uint32_t viommu_type, uint32_t hwpt_id,\n+ void *data_ptr, uint32_t data_len,\n uint32_t *out_hwpt, Error **errp);\n \n bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id,\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex 20d4186f29..9b07ac19c2 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -470,6 +470,7 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *be, uint32_t id,\n \n bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id,\n uint32_t viommu_type, uint32_t hwpt_id,\n+ void *data_ptr, uint32_t data_len,\n uint32_t *out_viommu_id, Error **errp)\n {\n int ret;\n@@ -478,11 +479,14 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id,\n .type = viommu_type,\n .dev_id = dev_id,\n .hwpt_id = hwpt_id,\n+ .data_len = data_len,\n+ .data_uptr = (uintptr_t)data_ptr,\n };\n \n ret = ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu);\n \n trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_id,\n+ (uintptr_t)data_ptr, data_len,\n alloc_viommu.out_viommu_id, ret);\n if (ret) {\n error_setg_errno(errp, errno, \"IOMMU_VIOMMU_ALLOC failed\");\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex d68d4141a0..c356ff9708 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -578,8 +578,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n IOMMUFDViommu *viommu;\n \n if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,\n- IOMMU_VIOMMU_TYPE_ARM_SMMUV3,\n- s2_hwpt_id, &viommu_id, errp)) {\n+ IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwpt_id,\n+ NULL, 0, &viommu_id, errp)) {\n return false;\n }\n \ndiff --git a/backends/trace-events b/backends/trace-events\nindex b9365113e7..3ba0c3503c 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -21,7 +21,7 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret) \" iommufd=%d id=%d (%\n iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int ret) \" iommufd=%d hwpt=%u enable=%d (%d)\"\n iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t iova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) \" iommufd=%d hwpt=%u iova=0x%\"PRIx64\" size=0x%\"PRIx64\" flags=0x%\"PRIx64\" page_size=0x%\"PRIx64\" (%d)\"\n iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_type, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t data_ptr, int ret) \" iommufd=%d id=%u data_type=%u entry_len=%u entry_num=%u done_num=%u data_ptr=0x%\"PRIx64\" (%d)\"\n-iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, uint32_t hwpt_id, uint32_t viommu_id, int ret) \" iommufd=%d type=%u dev_id=%u hwpt_id=%u viommu_id=%u (%d)\"\n+iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id, int ret) \" iommufd=%d type=%u dev_id=%u hwpt_id=%u data_ptr=0x%\"PRIx64\" data_len=0x%x viommu_id=%u (%d)\"\n iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_id, uint64_t virt_id, uint32_t vdev_id, int ret) \" iommufd=%d dev_id=%u viommu_id=%u virt_id=0x%\"PRIx64\" vdev_id=%u (%d)\"\n iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type, uint32_t veventq_id, uint32_t veventq_fd, int ret) \" iommufd=%d viommu_id=%u type=%u veventq_id=%u veventq_fd=%u (%d)\"\n \n","prefixes":["v4","02/31"]}