{"id":2222606,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2222606/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073215.29968-1-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260413073215.29968-1-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-13T07:32:15","name":"[for-11.1] linux-user/arm: Remove nwfpe","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"844d20122f7911bd14274fb99f92c1ab285db883","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073215.29968-1-richard.henderson@linaro.org/mbox/","series":[{"id":499656,"url":"http://patchwork.ozlabs.org/api/1.2/series/499656/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499656","date":"2026-04-13T07:32:15","name":"[for-11.1] linux-user/arm: Remove nwfpe","version":1,"mbox":"http://patchwork.ozlabs.org/series/499656/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222606/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222606/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZnS8hJEx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvJzW3Hwdz1xtJ\n\tfor ; Mon, 13 Apr 2026 17:33:11 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCBme-0005vs-Ud; Mon, 13 Apr 2026 03:32:36 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCBmY-0005vY-KI\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 03:32:32 -0400","from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wCBmT-0003ex-KA\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 03:32:30 -0400","by mail-pg1-x534.google.com with SMTP id\n 41be03b00d2f7-c76b0cda2aeso1653524a12.2\n for ; Mon, 13 Apr 2026 00:32:24 -0700 (PDT)","from stoup.. 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helo=mail-pg1-x534.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This emulation is present in the linux kernel only for\na very restricted set of configurations:\n\nconfig FPE_NWFPE\n bool \"NWFPE math emulation\"\n depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL\n\nEABI is the default for all armv6 capable kernels, so this\nisn't enabled in practice for some time.\n\nGCC removed support for the FPA11 somewhere before gcc-5.\n\nThe code within nwfpe is not thread-safe, using several\nglobal variables.\n\nSigned-off-by: Richard Henderson \n---\n linux-user/arm/nwfpe/fpa11.h | 126 ---------\n linux-user/arm/nwfpe/fpopcode.h | 390 ---------------------------\n linux-user/arm/nwfpe/fpsr.h | 107 --------\n linux-user/qemu.h | 11 -\n linux-user/arm/cpu_loop.c | 59 ----\n linux-user/arm/nwfpe/double_cpdo.c | 296 --------------------\n linux-user/arm/nwfpe/extended_cpdo.c | 273 -------------------\n linux-user/arm/nwfpe/fpa11.c | 270 -------------------\n linux-user/arm/nwfpe/fpa11_cpdo.c | 113 --------\n linux-user/arm/nwfpe/fpa11_cpdt.c | 382 --------------------------\n linux-user/arm/nwfpe/fpa11_cprt.c | 284 -------------------\n linux-user/arm/nwfpe/fpopcode.c | 91 -------\n linux-user/arm/nwfpe/single_cpdo.c | 253 -----------------\n linux-user/arm/meson.build | 2 -\n linux-user/arm/nwfpe/fpa11.inl | 50 ----\n linux-user/arm/nwfpe/meson.build | 10 -\n 16 files changed, 2717 deletions(-)\n delete mode 100644 linux-user/arm/nwfpe/fpa11.h\n delete mode 100644 linux-user/arm/nwfpe/fpopcode.h\n delete mode 100644 linux-user/arm/nwfpe/fpsr.h\n delete mode 100644 linux-user/arm/nwfpe/double_cpdo.c\n delete mode 100644 linux-user/arm/nwfpe/extended_cpdo.c\n delete mode 100644 linux-user/arm/nwfpe/fpa11.c\n delete mode 100644 linux-user/arm/nwfpe/fpa11_cpdo.c\n delete mode 100644 linux-user/arm/nwfpe/fpa11_cpdt.c\n delete mode 100644 linux-user/arm/nwfpe/fpa11_cprt.c\n delete mode 100644 linux-user/arm/nwfpe/fpopcode.c\n delete mode 100644 linux-user/arm/nwfpe/single_cpdo.c\n delete mode 100644 linux-user/arm/nwfpe/fpa11.inl\n delete mode 100644 linux-user/arm/nwfpe/meson.build","diff":"diff --git a/linux-user/arm/nwfpe/fpa11.h b/linux-user/arm/nwfpe/fpa11.h\ndeleted file mode 100644\nindex d459c5da02..0000000000\n--- a/linux-user/arm/nwfpe/fpa11.h\n+++ /dev/null\n@@ -1,126 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.com, 1998-1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#ifndef FPA11_H\n-#define FPA11_H\n-\n-#include \"cpu.h\"\n-\n-#define GET_FPA11() (qemufpa)\n-\n-/*\n- * The processes registers are always at the very top of the 8K\n- * stack+task struct. Use the same method as 'current' uses to\n- * reach them.\n- */\n-extern CPUARMState *user_registers;\n-\n-#define GET_USERREG() (user_registers)\n-\n-/* Need task_struct */\n-//#include \n-\n-/* includes */\n-#include \"fpsr.h\"\t\t/* FP control and status register definitions */\n-#include \"fpu/softfloat.h\"\n-\n-#define\t\ttypeNone\t\t0x00\n-#define\t\ttypeSingle\t\t0x01\n-#define\t\ttypeDouble\t\t0x02\n-#define\t\ttypeExtended\t\t0x03\n-\n-/*\n- * This must be no more and no less than 12 bytes.\n- */\n-typedef union tagFPREG {\n- floatx80 fExtended;\n- float64 fDouble;\n- float32 fSingle;\n-} FPREG;\n-\n-/*\n- * FPA11 device model.\n- *\n- * This structure is exported to user space. Do not re-order.\n- * Only add new stuff to the end, and do not change the size of\n- * any element. Elements of this structure are used by user\n- * space, and must match struct user_fp in include/asm-arm/user.h.\n- * We include the byte offsets below for documentation purposes.\n- *\n- * The size of this structure and FPREG are checked by fpmodule.c\n- * on initialisation. If the rules have been broken, NWFPE will\n- * not initialise.\n- */\n-typedef struct tagFPA11 {\n-/* 0 */ FPREG fpreg[8];\t\t/* 8 floating point registers */\n-/* 96 */ FPSR fpsr;\t\t\t/* floating point status register */\n-/* 100 */ FPCR fpcr;\t\t\t/* floating point control register */\n-/* 104 */ unsigned char fType[8];\t/* type of floating point value held in\n-\t\t\t\t\t floating point registers. One of none\n-\t\t\t\t\t single, double or extended. */\n-/* 112 */ int initflag;\t\t/* this is special. The kernel guarantees\n-\t\t\t\t\t to set it to 0 when a thread is launched,\n-\t\t\t\t\t so we can use it to detect whether this\n-\t\t\t\t\t instance of the emulator needs to be\n-\t\t\t\t\t initialised. */\n- float_status fp_status; /* QEMU float emulator status */\n-} FPA11;\n-\n-extern FPA11* qemufpa;\n-\n-void resetFPA11(void);\n-void SetRoundingMode(const unsigned int);\n-void SetRoundingPrecision(const unsigned int);\n-\n-static inline unsigned int readRegister(unsigned int reg)\n-{\n- return (user_registers->regs[(reg)]);\n-}\n-\n-static inline void writeRegister(unsigned int x, unsigned int y)\n-{\n-#if 0\n-\tprintf(\"writing %d to r%d\\n\",y,x);\n-#endif\n- user_registers->regs[(x)]=(y);\n-}\n-\n-static inline void writeConditionCodes(unsigned int x)\n-{\n- cpsr_write(user_registers, x, CPSR_NZCV, CPSRWriteByInstr);\n-}\n-\n-#define ARM_REG_PC 15\n-\n-unsigned int EmulateAll(unsigned int opcode, FPA11* qfpa, CPUARMState* qregs);\n-\n-unsigned int EmulateCPDO(const unsigned int);\n-unsigned int EmulateCPDT(const unsigned int);\n-unsigned int EmulateCPRT(const unsigned int);\n-\n-unsigned int SingleCPDO(const unsigned int opcode);\n-unsigned int DoubleCPDO(const unsigned int opcode);\n-unsigned int ExtendedCPDO(const unsigned int opcode);\n-\n-\n-/* included only for get_user/put_user macros */\n-#include \"qemu.h\"\n-\n-#endif\ndiff --git a/linux-user/arm/nwfpe/fpopcode.h b/linux-user/arm/nwfpe/fpopcode.h\ndeleted file mode 100644\nindex 06cd909850..0000000000\n--- a/linux-user/arm/nwfpe/fpopcode.h\n+++ /dev/null\n@@ -1,390 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#ifndef FPOPCODE_H\n-#define FPOPCODE_H\n-\n-/*\n-ARM Floating Point Instruction Classes\n-| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |\n-|c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT\n-|c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT\n-| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |\n-|c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO\n-|c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT\n-|c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons\n-| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |\n-\n-CPDT\t\tdata transfer instructions\n-\t\tLDF, STF, LFM, SFM\n-\n-CPDO\t\tdyadic arithmetic instructions\n-\t\tADF, MUF, SUF, RSF, DVF, RDF,\n-\t\tPOW, RPW, RMF, FML, FDV, FRD, POL\n-\n-CPDO\t\tmonadic arithmetic instructions\n-\t\tMVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,\n-\t\tSIN, COS, TAN, ASN, ACS, ATN, URD, NRM\n-\n-CPRT\t\tjoint arithmetic/data transfer instructions\n-\t\tFIX (arithmetic followed by load/store)\n-\t\tFLT (load/store followed by arithmetic)\n-\t\tCMF, CNF CMFE, CNFE (comparisons)\n-\t\tWFS, RFS (write/read floating point status register)\n-\t\tWFC, RFC (write/read floating point control register)\n-\n-cond\t\tcondition codes\n-P\t\tpre/post index bit: 0 = postindex, 1 = preindex\n-U\t\tup/down bit: 0 = stack grows down, 1 = stack grows up\n-W\t\twrite back bit: 1 = update base register (Rn)\n-L\t\tload/store bit: 0 = store, 1 = load\n-Rn\t\tbase register\n-Rd\t\tdestination/source register\n-Fd\t\tfloating point destination register\n-Fn\t\tfloating point source register\n-Fm\t\tfloating point source register or floating point constant\n-\n-uv\t\ttransfer length (TABLE 1)\n-wx\t\tregister count (TABLE 2)\n-abcd\t\tarithmetic opcode (TABLES 3 & 4)\n-ef\t\tdestination size (rounding precision) (TABLE 5)\n-gh\t\trounding mode (TABLE 6)\n-j\t\tdyadic/monadic bit: 0 = dyadic, 1 = monadic\n-i \t\tconstant bit: 1 = constant (TABLE 6)\n-*/\n-\n-/*\n-TABLE 1\n-+-------------------------+---+---+---------+---------+\n-| Precision | u | v | FPSR.EP | length |\n-+-------------------------+---+---+---------+---------+\n-| Single | 0 | 0 | x | 1 words |\n-| Double | 1 | 1 | x | 2 words |\n-| Extended | 1 | 1 | x | 3 words |\n-| Packed decimal | 1 | 1 | 0 | 3 words |\n-| Expanded packed decimal | 1 | 1 | 1 | 4 words |\n-+-------------------------+---+---+---------+---------+\n-Note: x = don't care\n-*/\n-\n-/*\n-TABLE 2\n-+---+---+---------------------------------+\n-| w | x | Number of registers to transfer |\n-+---+---+---------------------------------+\n-| 0 | 1 | 1 |\n-| 1 | 0 | 2 |\n-| 1 | 1 | 3 |\n-| 0 | 0 | 4 |\n-+---+---+---------------------------------+\n-*/\n-\n-/*\n-TABLE 3: Dyadic Floating Point Opcodes\n-+---+---+---+---+----------+-----------------------+-----------------------+\n-| a | b | c | d | Mnemonic | Description | Operation |\n-+---+---+---+---+----------+-----------------------+-----------------------+\n-| 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |\n-| 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |\n-| 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |\n-| 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |\n-| 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |\n-| 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |\n-| 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |\n-| 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |\n-| 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |\n-| 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |\n-| 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |\n-| 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |\n-| 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |\n-| 1 | 1 | 0 | 1 | | undefined instruction | trap |\n-| 1 | 1 | 1 | 0 | | undefined instruction | trap |\n-| 1 | 1 | 1 | 1 | | undefined instruction | trap |\n-+---+---+---+---+----------+-----------------------+-----------------------+\n-Note: POW, RPW, POL are deprecated, and are available for backwards\n- compatibility only.\n-*/\n-\n-/*\n-TABLE 4: Monadic Floating Point Opcodes\n-+---+---+---+---+----------+-----------------------+-----------------------+\n-| a | b | c | d | Mnemonic | Description | Operation |\n-+---+---+---+---+----------+-----------------------+-----------------------+\n-| 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |\n-| 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |\n-| 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |\n-| 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |\n-| 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |\n-| 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |\n-| 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |\n-| 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |\n-| 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |\n-| 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |\n-| 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |\n-| 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |\n-| 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |\n-| 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |\n-| 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |\n-| 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |\n-+---+---+---+---+----------+-----------------------+-----------------------+\n-Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are\n- available for backwards compatibility only.\n-*/\n-\n-/*\n-TABLE 5\n-+-------------------------+---+---+\n-| Rounding Precision | e | f |\n-+-------------------------+---+---+\n-| IEEE Single precision | 0 | 0 |\n-| IEEE Double precision | 0 | 1 |\n-| IEEE Extended precision | 1 | 0 |\n-| undefined (trap) | 1 | 1 |\n-+-------------------------+---+---+\n-*/\n-\n-/*\n-TABLE 5\n-+---------------------------------+---+---+\n-| Rounding Mode | g | h |\n-+---------------------------------+---+---+\n-| Round to nearest (default) | 0 | 0 |\n-| Round toward plus infinity | 0 | 1 |\n-| Round toward negative infinity | 1 | 0 |\n-| Round toward zero | 1 | 1 |\n-+---------------------------------+---+---+\n-*/\n-\n-/*\n-===\n-=== Definitions for load and store instructions\n-===\n-*/\n-\n-/* bit masks */\n-#define BIT_PREINDEX\t0x01000000\n-#define BIT_UP\t\t0x00800000\n-#define BIT_WRITE_BACK\t0x00200000\n-#define BIT_LOAD\t0x00100000\n-\n-/* masks for load/store */\n-#define MASK_CPDT\t\t0x0c000000 /* data processing opcode */\n-#define MASK_OFFSET\t\t0x000000ff\n-#define MASK_TRANSFER_LENGTH\t0x00408000\n-#define MASK_REGISTER_COUNT\tMASK_TRANSFER_LENGTH\n-#define MASK_COPROCESSOR\t0x00000f00\n-\n-/* Tests for transfer length */\n-#define TRANSFER_SINGLE\t\t0x00000000\n-#define TRANSFER_DOUBLE\t\t0x00008000\n-#define TRANSFER_EXTENDED\t0x00400000\n-#define TRANSFER_PACKED\t\tMASK_TRANSFER_LENGTH\n-\n-/* Get the coprocessor number from the opcode. */\n-#define getCoprocessorNumber(opcode)\t((opcode & MASK_COPROCESSOR) >> 8)\n-\n-/* Get the offset from the opcode. */\n-#define getOffset(opcode)\t\t(opcode & MASK_OFFSET)\n-\n-/* Tests for specific data transfer load/store opcodes. */\n-#define TEST_OPCODE(opcode,mask)\t(((opcode) & (mask)) == (mask))\n-\n-#define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)\n-#define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)\n-\n-#define LDF_OP(opcode)\t(LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))\n-#define LFM_OP(opcode)\t(LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))\n-#define STF_OP(opcode)\t(STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))\n-#define SFM_OP(opcode)\t(STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))\n-\n-#define PREINDEXED(opcode)\t\t((opcode & BIT_PREINDEX) != 0)\n-#define POSTINDEXED(opcode)\t\t((opcode & BIT_PREINDEX) == 0)\n-#define BIT_UP_SET(opcode)\t\t((opcode & BIT_UP) != 0)\n-#define BIT_UP_CLEAR(opcode)\t\t((opcode & BIT_DOWN) == 0)\n-#define WRITE_BACK(opcode)\t\t((opcode & BIT_WRITE_BACK) != 0)\n-#define LOAD(opcode)\t\t\t((opcode & BIT_LOAD) != 0)\n-#define STORE(opcode)\t\t\t((opcode & BIT_LOAD) == 0)\n-\n-/*\n-===\n-=== Definitions for arithmetic instructions\n-===\n-*/\n-/* bit masks */\n-#define BIT_MONADIC\t0x00008000\n-#define BIT_CONSTANT\t0x00000008\n-\n-#define CONSTANT_FM(opcode)\t\t((opcode & BIT_CONSTANT) != 0)\n-#define MONADIC_INSTRUCTION(opcode)\t((opcode & BIT_MONADIC) != 0)\n-\n-/* instruction identification masks */\n-#define MASK_CPDO\t\t0x0e000000 /* arithmetic opcode */\n-#define MASK_ARITHMETIC_OPCODE\t0x00f08000\n-#define MASK_DESTINATION_SIZE\t0x00080080\n-\n-/* dyadic arithmetic opcodes. */\n-#define ADF_CODE\t0x00000000\n-#define MUF_CODE\t0x00100000\n-#define SUF_CODE\t0x00200000\n-#define RSF_CODE\t0x00300000\n-#define DVF_CODE\t0x00400000\n-#define RDF_CODE\t0x00500000\n-#define POW_CODE\t0x00600000\n-#define RPW_CODE\t0x00700000\n-#define RMF_CODE\t0x00800000\n-#define FML_CODE\t0x00900000\n-#define FDV_CODE\t0x00a00000\n-#define FRD_CODE\t0x00b00000\n-#define POL_CODE\t0x00c00000\n-/* 0x00d00000 is an invalid dyadic arithmetic opcode */\n-/* 0x00e00000 is an invalid dyadic arithmetic opcode */\n-/* 0x00f00000 is an invalid dyadic arithmetic opcode */\n-\n-/* monadic arithmetic opcodes. */\n-#define MVF_CODE\t0x00008000\n-#define MNF_CODE\t0x00108000\n-#define ABS_CODE\t0x00208000\n-#define RND_CODE\t0x00308000\n-#define SQT_CODE\t0x00408000\n-#define LOG_CODE\t0x00508000\n-#define LGN_CODE\t0x00608000\n-#define EXP_CODE\t0x00708000\n-#define SIN_CODE\t0x00808000\n-#define COS_CODE\t0x00908000\n-#define TAN_CODE\t0x00a08000\n-#define ASN_CODE\t0x00b08000\n-#define ACS_CODE\t0x00c08000\n-#define ATN_CODE\t0x00d08000\n-#define URD_CODE\t0x00e08000\n-#define NRM_CODE\t0x00f08000\n-\n-/*\n-===\n-=== Definitions for register transfer and comparison instructions\n-===\n-*/\n-\n-#define MASK_CPRT\t\t0x0e000010 /* register transfer opcode */\n-#define MASK_CPRT_CODE\t\t0x00f00000\n-#define FLT_CODE\t\t0x00000000\n-#define FIX_CODE\t\t0x00100000\n-#define WFS_CODE\t\t0x00200000\n-#define RFS_CODE\t\t0x00300000\n-#define WFC_CODE\t\t0x00400000\n-#define RFC_CODE\t\t0x00500000\n-#define CMF_CODE\t\t0x00900000\n-#define CNF_CODE\t\t0x00b00000\n-#define CMFE_CODE\t\t0x00d00000\n-#define CNFE_CODE\t\t0x00f00000\n-\n-/*\n-===\n-=== Common definitions\n-===\n-*/\n-\n-/* register masks */\n-#define MASK_Rd\t\t0x0000f000\n-#define MASK_Rn\t\t0x000f0000\n-#define MASK_Fd\t\t0x00007000\n-#define MASK_Fm\t\t0x00000007\n-#define MASK_Fn\t\t0x00070000\n-\n-/* condition code masks */\n-#define CC_MASK\t\t0xf0000000\n-#define CC_NEGATIVE\t0x80000000\n-#define CC_ZERO\t\t0x40000000\n-#define CC_CARRY\t0x20000000\n-#define CC_OVERFLOW\t0x10000000\n-#define CC_EQ\t\t0x00000000\n-#define CC_NE\t\t0x10000000\n-#define CC_CS\t\t0x20000000\n-#define CC_HS\t\tCC_CS\n-#define CC_CC\t\t0x30000000\n-#define CC_LO\t\tCC_CC\n-#define CC_MI\t\t0x40000000\n-#define CC_PL\t\t0x50000000\n-#define CC_VS\t\t0x60000000\n-#define CC_VC\t\t0x70000000\n-#define CC_HI\t\t0x80000000\n-#define CC_LS\t\t0x90000000\n-#define CC_GE\t\t0xa0000000\n-#define CC_LT\t\t0xb0000000\n-#define CC_GT\t\t0xc0000000\n-#define CC_LE\t\t0xd0000000\n-#define CC_AL\t\t0xe0000000\n-#define CC_NV\t\t0xf0000000\n-\n-/* rounding masks/values */\n-#define MASK_ROUNDING_MODE\t0x00000060\n-#define ROUND_TO_NEAREST\t0x00000000\n-#define ROUND_TO_PLUS_INFINITY\t0x00000020\n-#define ROUND_TO_MINUS_INFINITY\t0x00000040\n-#define ROUND_TO_ZERO\t\t0x00000060\n-\n-#define MASK_ROUNDING_PRECISION\t0x00080080\n-#define ROUND_SINGLE\t\t0x00000000\n-#define ROUND_DOUBLE\t\t0x00000080\n-#define ROUND_EXTENDED\t\t0x00080000\n-\n-/* Get the condition code from the opcode. */\n-#define getCondition(opcode)\t\t(opcode >> 28)\n-\n-/* Get the source register from the opcode. */\n-#define getRn(opcode)\t\t\t((opcode & MASK_Rn) >> 16)\n-\n-/* Get the destination floating point register from the opcode. */\n-#define getFd(opcode)\t\t\t((opcode & MASK_Fd) >> 12)\n-\n-/* Get the first source floating point register from the opcode. */\n-#define getFn(opcode)\t\t((opcode & MASK_Fn) >> 16)\n-\n-/* Get the second source floating point register from the opcode. */\n-#define getFm(opcode)\t\t(opcode & MASK_Fm)\n-\n-/* Get the destination register from the opcode. */\n-#define getRd(opcode)\t\t((opcode & MASK_Rd) >> 12)\n-\n-/* Get the rounding mode from the opcode. */\n-#define getRoundingMode(opcode)\t\t((opcode & MASK_ROUNDING_MODE) >> 5)\n-\n-extern const floatx80 floatx80Constant[];\n-extern const float64 float64Constant[];\n-extern const float32 float32Constant[];\n-\n-static inline floatx80 getExtendedConstant(const unsigned int nIndex)\n-{\n- return floatx80Constant[nIndex];\n-}\n-\n-static inline float64 getDoubleConstant(const unsigned int nIndex)\n-{\n- return float64Constant[nIndex];\n-}\n-\n-static inline float32 getSingleConstant(const unsigned int nIndex)\n-{\n- return float32Constant[nIndex];\n-}\n-\n-unsigned int getRegisterCount(const unsigned int opcode);\n-unsigned int getDestinationSize(const unsigned int opcode);\n-\n-#endif\ndiff --git a/linux-user/arm/nwfpe/fpsr.h b/linux-user/arm/nwfpe/fpsr.h\ndeleted file mode 100644\nindex 8c978f0b8f..0000000000\n--- a/linux-user/arm/nwfpe/fpsr.h\n+++ /dev/null\n@@ -1,107 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.com, 1998-1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#ifndef FPSR_H\n-#define FPSR_H\n-\n-/*\n-The FPSR is a 32 bit register consisting of 4 parts, each exactly\n-one byte.\n-\n-\tSYSTEM ID\n-\tEXCEPTION TRAP ENABLE BYTE\n-\tSYSTEM CONTROL BYTE\n-\tCUMULATIVE EXCEPTION FLAGS BYTE\n-\n-The FPCR is a 32 bit register consisting of bit flags.\n-*/\n-\n-/* SYSTEM ID\n-------------\n-Note: the system id byte is read only */\n-\n-typedef unsigned int FPSR; /* type for floating point status register */\n-typedef unsigned int FPCR; /* type for floating point control register */\n-\n-#define MASK_SYSID\t\t0xff000000\n-#define BIT_HARDWARE\t\t0x80000000\n-#define FP_EMULATOR\t\t0x01000000\t/* System ID for emulator */\n-#define FP_ACCELERATOR\t\t0x81000000\t/* System ID for FPA11 */\n-\n-/* EXCEPTION TRAP ENABLE BYTE\n------------------------------ */\n-\n-#define MASK_TRAP_ENABLE\t0x00ff0000\n-#define MASK_TRAP_ENABLE_STRICT\t0x001f0000\n-#define BIT_IXE\t\t0x00100000 /* inexact exception enable */\n-#define BIT_UFE\t\t0x00080000 /* underflow exception enable */\n-#define BIT_OFE\t\t0x00040000 /* overflow exception enable */\n-#define BIT_DZE\t\t0x00020000 /* divide by zero exception enable */\n-#define BIT_IOE\t\t0x00010000 /* invalid operation exception enable */\n-\n-/* SYSTEM CONTROL BYTE\n----------------------- */\n-\n-#define MASK_SYSTEM_CONTROL\t0x0000ff00\n-#define MASK_TRAP_STRICT\t0x00001f00\n-\n-#define BIT_AC\t0x00001000\t/* use alternative C-flag definition\n-\t\t\t\t for compares */\n-#define BIT_EP\t0x00000800\t/* use expanded packed decimal format */\n-#define BIT_SO\t0x00000400\t/* select synchronous operation of FPA */\n-#define BIT_NE\t0x00000200\t/* NaN exception bit */\n-#define BIT_ND\t0x00000100\t/* no denormalized numbers bit */\n-\n-/* CUMULATIVE EXCEPTION FLAGS BYTE\n----------------------------------- */\n-\n-#define MASK_EXCEPTION_FLAGS\t\t0x000000ff\n-#define MASK_EXCEPTION_FLAGS_STRICT\t0x0000001f\n-\n-#define BIT_IXC\t\t0x00000010\t/* inexact exception flag */\n-#define BIT_UFC\t\t0x00000008\t/* underflow exception flag */\n-#define BIT_OFC\t\t0x00000004\t/* overfloat exception flag */\n-#define BIT_DZC\t\t0x00000002\t/* divide by zero exception flag */\n-#define BIT_IOC\t\t0x00000001\t/* invalid operation exception flag */\n-\n-/* Floating Point Control Register\n-----------------------------------*/\n-\n-#define BIT_RU\t\t0x80000000\t/* rounded up bit */\n-#define BIT_IE\t\t0x10000000\t/* inexact bit */\n-#define BIT_MO\t\t0x08000000\t/* mantissa overflow bit */\n-#define BIT_EO\t\t0x04000000\t/* exponent overflow bit */\n-#define BIT_SB\t\t0x00000800\t/* store bounce */\n-#define BIT_AB\t\t0x00000400\t/* arithmetic bounce */\n-#define BIT_RE\t\t0x00000200\t/* rounding exception */\n-#define BIT_DA\t\t0x00000100\t/* disable FPA */\n-\n-#define MASK_OP\t\t0x00f08010\t/* AU operation code */\n-#define MASK_PR\t\t0x00080080\t/* AU precision */\n-#define MASK_S1\t\t0x00070000\t/* AU source register 1 */\n-#define MASK_S2\t\t0x00000007\t/* AU source register 2 */\n-#define MASK_DS\t\t0x00007000\t/* AU destination register */\n-#define MASK_RM\t\t0x00000060\t/* AU rounding mode */\n-#define MASK_ALU\t0x9cfff2ff\t/* only ALU can write these bits */\n-#define MASK_RESET\t0x00000d00\t/* bits set on reset, all others cleared */\n-#define MASK_WFC\tMASK_RESET\n-#define MASK_RFC\t~MASK_RESET\n-\n-#endif\ndiff --git a/linux-user/qemu.h b/linux-user/qemu.h\nindex cfe5f45fc4..21afce4088 100644\n--- a/linux-user/qemu.h\n+++ b/linux-user/qemu.h\n@@ -87,11 +87,6 @@ struct vm86_saved_state {\n };\n #endif\n \n-#if defined(TARGET_ARM) && defined(TARGET_ABI32)\n-/* FPU emulator */\n-#include \"nwfpe/fpa11.h\"\n-#endif\n-\n struct emulated_sigtable {\n int pending; /* true if signal is pending */\n target_siginfo_t info;\n@@ -99,12 +94,6 @@ struct emulated_sigtable {\n \n struct TaskState {\n pid_t ts_tid; /* tid (or pid) of this task */\n-#ifdef TARGET_ARM\n-# ifdef TARGET_ABI32\n- /* FPA state */\n- FPA11 fpa;\n-# endif\n-#endif\n #if defined(TARGET_ARM) || defined(TARGET_RISCV)\n int swi_errno;\n #endif\ndiff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c\nindex 19874f4c72..36f82541c7 100644\n--- a/linux-user/arm/cpu_loop.c\n+++ b/linux-user/arm/cpu_loop.c\n@@ -212,61 +212,6 @@ static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb)\n }\n }\n \n-static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode)\n-{\n- TaskState *ts = get_task_state(env_cpu(env));\n- int rc = EmulateAll(opcode, &ts->fpa, env);\n- int raise, enabled;\n-\n- if (rc == 0) {\n- /* Illegal instruction */\n- return false;\n- }\n- if (rc > 0) {\n- /* Everything ok. */\n- env->regs[15] += 4;\n- return true;\n- }\n-\n- /* FP exception */\n- rc = -rc;\n- raise = 0;\n-\n- /* Translate softfloat flags to FPSR flags */\n- if (rc & float_flag_invalid) {\n- raise |= BIT_IOC;\n- }\n- if (rc & float_flag_divbyzero) {\n- raise |= BIT_DZC;\n- }\n- if (rc & float_flag_overflow) {\n- raise |= BIT_OFC;\n- }\n- if (rc & float_flag_underflow) {\n- raise |= BIT_UFC;\n- }\n- if (rc & float_flag_inexact) {\n- raise |= BIT_IXC;\n- }\n-\n- /* Accumulate unenabled exceptions */\n- enabled = ts->fpa.fpsr >> 16;\n- ts->fpa.fpsr |= raise & ~enabled;\n-\n- if (raise & enabled) {\n- /*\n- * The kernel's nwfpe emulator does not pass a real si_code.\n- * It merely uses send_sig(SIGFPE, current, 1), which results in\n- * __send_signal() filling out SI_KERNEL with pid and uid 0 (under\n- * the \"SEND_SIG_PRIV\" case). That's what our force_sig() does.\n- */\n- force_sig(TARGET_SIGFPE);\n- } else {\n- env->regs[15] += 4;\n- }\n- return true;\n-}\n-\n void cpu_loop(CPUARMState *env)\n {\n CPUState *cs = env_cpu(env);\n@@ -302,10 +247,6 @@ void cpu_loop(CPUARMState *env)\n goto excp_debug;\n }\n \n- if (!env->thumb && emulate_arm_fpa11(env, opcode)) {\n- break;\n- }\n-\n force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN,\n env->regs[15]);\n }\ndiff --git a/linux-user/arm/nwfpe/double_cpdo.c b/linux-user/arm/nwfpe/double_cpdo.c\ndeleted file mode 100644\nindex d45ece2e2f..0000000000\n--- a/linux-user/arm/nwfpe/double_cpdo.c\n+++ /dev/null\n@@ -1,296 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpu/softfloat.h\"\n-#include \"fpopcode.h\"\n-\n-float64 float64_exp(float64 Fm);\n-float64 float64_ln(float64 Fm);\n-float64 float64_sin(float64 rFm);\n-float64 float64_cos(float64 rFm);\n-float64 float64_arcsin(float64 rFm);\n-float64 float64_arctan(float64 rFm);\n-float64 float64_log(float64 rFm);\n-float64 float64_tan(float64 rFm);\n-float64 float64_arccos(float64 rFm);\n-float64 float64_pow(float64 rFn,float64 rFm);\n-float64 float64_pol(float64 rFn,float64 rFm);\n-\n-unsigned int DoubleCPDO(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- float64 rFm, rFn = float64_zero;\n- unsigned int Fd, Fm, Fn, nRc = 1;\n-\n- //printk(\"DoubleCPDO(0x%08x)\\n\",opcode);\n-\n- Fm = getFm(opcode);\n- if (CONSTANT_FM(opcode))\n- {\n- rFm = getDoubleConstant(Fm);\n- }\n- else\n- {\n- switch (fpa11->fType[Fm])\n- {\n- case typeSingle:\n- rFm = float32_to_float64(fpa11->fpreg[Fm].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- rFm = fpa11->fpreg[Fm].fDouble;\n- break;\n-\n- case typeExtended:\n- // !! patb\n-\t //printk(\"not implemented! why not?\\n\");\n- //!! ScottB\n- // should never get here, if extended involved\n- // then other operand should be promoted then\n- // ExtendedCPDO called.\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- if (!MONADIC_INSTRUCTION(opcode))\n- {\n- Fn = getFn(opcode);\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- rFn = float32_to_float64(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- rFn = fpa11->fpreg[Fn].fDouble;\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- Fd = getFd(opcode);\n- /* !! this switch isn't optimized; better (opcode & MASK_ARITHMETIC_OPCODE)>>24, sort of */\n- switch (opcode & MASK_ARITHMETIC_OPCODE)\n- {\n- /* dyadic opcodes */\n- case ADF_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_add(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case MUF_CODE:\n- case FML_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_mul(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case SUF_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_sub(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case RSF_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_sub(rFm,rFn, &fpa11->fp_status);\n- break;\n-\n- case DVF_CODE:\n- case FDV_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_div(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case RDF_CODE:\n- case FRD_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_div(rFm,rFn, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case POW_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_pow(rFn,rFm);\n- break;\n-\n- case RPW_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_pow(rFm,rFn);\n- break;\n-#endif\n-\n- case RMF_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_rem(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case POL_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_pol(rFn,rFm);\n- break;\n-#endif\n-\n- /* monadic opcodes */\n- case MVF_CODE:\n- fpa11->fpreg[Fd].fDouble = rFm;\n- break;\n-\n- case MNF_CODE:\n- {\n- unsigned int *p = (unsigned int*)&rFm;\n-#if HOST_BIG_ENDIAN\n- p[0] ^= 0x80000000;\n-#else\n- p[1] ^= 0x80000000;\n-#endif\n- fpa11->fpreg[Fd].fDouble = rFm;\n- }\n- break;\n-\n- case ABS_CODE:\n- {\n- unsigned int *p = (unsigned int*)&rFm;\n-#if HOST_BIG_ENDIAN\n- p[0] &= 0x7fffffff;\n-#else\n- p[1] &= 0x7fffffff;\n-#endif\n- fpa11->fpreg[Fd].fDouble = rFm;\n- }\n- break;\n-\n- case RND_CODE:\n- case URD_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_round_to_int(rFm, &fpa11->fp_status);\n- break;\n-\n- case SQT_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_sqrt(rFm, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case LOG_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_log(rFm);\n- break;\n-\n- case LGN_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_ln(rFm);\n- break;\n-\n- case EXP_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_exp(rFm);\n- break;\n-\n- case SIN_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_sin(rFm);\n- break;\n-\n- case COS_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_cos(rFm);\n- break;\n-\n- case TAN_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_tan(rFm);\n- break;\n-\n- case ASN_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_arcsin(rFm);\n- break;\n-\n- case ACS_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_arccos(rFm);\n- break;\n-\n- case ATN_CODE:\n- fpa11->fpreg[Fd].fDouble = float64_arctan(rFm);\n- break;\n-#endif\n-\n- case NRM_CODE:\n- break;\n-\n- default:\n- {\n- nRc = 0;\n- }\n- }\n-\n- if (0 != nRc) fpa11->fType[Fd] = typeDouble;\n- return nRc;\n-}\n-\n-#if 0\n-float64 float64_exp(float64 rFm)\n-{\n- return rFm;\n-//series\n-}\n-\n-float64 float64_ln(float64 rFm)\n-{\n- return rFm;\n-//series\n-}\n-\n-float64 float64_sin(float64 rFm)\n-{\n- return rFm;\n-//series\n-}\n-\n-float64 float64_cos(float64 rFm)\n-{\n- return rFm;\n- //series\n-}\n-\n-#if 0\n-float64 float64_arcsin(float64 rFm)\n-{\n-//series\n-}\n-\n-float64 float64_arctan(float64 rFm)\n-{\n- //series\n-}\n-#endif\n-\n-float64 float64_log(float64 rFm)\n-{\n- return float64_div(float64_ln(rFm),getDoubleConstant(7));\n-}\n-\n-float64 float64_tan(float64 rFm)\n-{\n- return float64_div(float64_sin(rFm),float64_cos(rFm));\n-}\n-\n-float64 float64_arccos(float64 rFm)\n-{\n-return rFm;\n- //return float64_sub(halfPi,float64_arcsin(rFm));\n-}\n-\n-float64 float64_pow(float64 rFn,float64 rFm)\n-{\n- return float64_exp(float64_mul(rFm,float64_ln(rFn)));\n-}\n-\n-float64 float64_pol(float64 rFn,float64 rFm)\n-{\n- return float64_arctan(float64_div(rFn,rFm));\n-}\n-#endif\ndiff --git a/linux-user/arm/nwfpe/extended_cpdo.c b/linux-user/arm/nwfpe/extended_cpdo.c\ndeleted file mode 100644\nindex 1c8a412292..0000000000\n--- a/linux-user/arm/nwfpe/extended_cpdo.c\n+++ /dev/null\n@@ -1,273 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpu/softfloat.h\"\n-#include \"fpopcode.h\"\n-\n-floatx80 floatx80_exp(floatx80 Fm);\n-floatx80 floatx80_ln(floatx80 Fm);\n-floatx80 floatx80_sin(floatx80 rFm);\n-floatx80 floatx80_cos(floatx80 rFm);\n-floatx80 floatx80_arcsin(floatx80 rFm);\n-floatx80 floatx80_arctan(floatx80 rFm);\n-floatx80 floatx80_log(floatx80 rFm);\n-floatx80 floatx80_tan(floatx80 rFm);\n-floatx80 floatx80_arccos(floatx80 rFm);\n-floatx80 floatx80_pow(floatx80 rFn,floatx80 rFm);\n-floatx80 floatx80_pol(floatx80 rFn,floatx80 rFm);\n-\n-unsigned int ExtendedCPDO(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- floatx80 rFm, rFn;\n- unsigned int Fd, Fm, Fn, nRc = 1;\n-\n- //printk(\"ExtendedCPDO(0x%08x)\\n\",opcode);\n-\n- Fm = getFm(opcode);\n- if (CONSTANT_FM(opcode))\n- {\n- rFm = getExtendedConstant(Fm);\n- }\n- else\n- {\n- switch (fpa11->fType[Fm])\n- {\n- case typeSingle:\n- rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble, &fpa11->fp_status);\n- break;\n-\n- case typeExtended:\n- rFm = fpa11->fpreg[Fm].fExtended;\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- if (!MONADIC_INSTRUCTION(opcode))\n- {\n- Fn = getFn(opcode);\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);\n- break;\n-\n- case typeExtended:\n- rFn = fpa11->fpreg[Fn].fExtended;\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- Fd = getFd(opcode);\n- switch (opcode & MASK_ARITHMETIC_OPCODE)\n- {\n- /* dyadic opcodes */\n- case ADF_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_add(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case MUF_CODE:\n- case FML_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_mul(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case SUF_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_sub(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case RSF_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_sub(rFm,rFn, &fpa11->fp_status);\n- break;\n-\n- case DVF_CODE:\n- case FDV_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_div(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case RDF_CODE:\n- case FRD_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_div(rFm,rFn, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case POW_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_pow(rFn,rFm);\n- break;\n-\n- case RPW_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_pow(rFm,rFn);\n- break;\n-#endif\n-\n- case RMF_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_rem(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case POL_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_pol(rFn,rFm);\n- break;\n-#endif\n-\n- /* monadic opcodes */\n- case MVF_CODE:\n- fpa11->fpreg[Fd].fExtended = rFm;\n- break;\n-\n- case MNF_CODE:\n- rFm.high ^= 0x8000;\n- fpa11->fpreg[Fd].fExtended = rFm;\n- break;\n-\n- case ABS_CODE:\n- rFm.high &= 0x7fff;\n- fpa11->fpreg[Fd].fExtended = rFm;\n- break;\n-\n- case RND_CODE:\n- case URD_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_round_to_int(rFm, &fpa11->fp_status);\n- break;\n-\n- case SQT_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_sqrt(rFm, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case LOG_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_log(rFm);\n- break;\n-\n- case LGN_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_ln(rFm);\n- break;\n-\n- case EXP_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_exp(rFm);\n- break;\n-\n- case SIN_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_sin(rFm);\n- break;\n-\n- case COS_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_cos(rFm);\n- break;\n-\n- case TAN_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_tan(rFm);\n- break;\n-\n- case ASN_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_arcsin(rFm);\n- break;\n-\n- case ACS_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_arccos(rFm);\n- break;\n-\n- case ATN_CODE:\n- fpa11->fpreg[Fd].fExtended = floatx80_arctan(rFm);\n- break;\n-#endif\n-\n- case NRM_CODE:\n- break;\n-\n- default:\n- {\n- nRc = 0;\n- }\n- }\n-\n- if (0 != nRc) fpa11->fType[Fd] = typeExtended;\n- return nRc;\n-}\n-\n-#if 0\n-floatx80 floatx80_exp(floatx80 Fm)\n-{\n-//series\n-}\n-\n-floatx80 floatx80_ln(floatx80 Fm)\n-{\n-//series\n-}\n-\n-floatx80 floatx80_sin(floatx80 rFm)\n-{\n-//series\n-}\n-\n-floatx80 floatx80_cos(floatx80 rFm)\n-{\n-//series\n-}\n-\n-floatx80 floatx80_arcsin(floatx80 rFm)\n-{\n-//series\n-}\n-\n-floatx80 floatx80_arctan(floatx80 rFm)\n-{\n- //series\n-}\n-\n-floatx80 floatx80_log(floatx80 rFm)\n-{\n- return floatx80_div(floatx80_ln(rFm),getExtendedConstant(7));\n-}\n-\n-floatx80 floatx80_tan(floatx80 rFm)\n-{\n- return floatx80_div(floatx80_sin(rFm),floatx80_cos(rFm));\n-}\n-\n-floatx80 floatx80_arccos(floatx80 rFm)\n-{\n- //return floatx80_sub(halfPi,floatx80_arcsin(rFm));\n-}\n-\n-floatx80 floatx80_pow(floatx80 rFn,floatx80 rFm)\n-{\n- return floatx80_exp(floatx80_mul(rFm,floatx80_ln(rFn)));\n-}\n-\n-floatx80 floatx80_pol(floatx80 rFn,floatx80 rFm)\n-{\n- return floatx80_arctan(floatx80_div(rFn,rFm));\n-}\n-#endif\ndiff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c\ndeleted file mode 100644\nindex 0f1afbd91d..0000000000\n--- a/linux-user/arm/nwfpe/fpa11.c\n+++ /dev/null\n@@ -1,270 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-\n-#include \"fpopcode.h\"\n-\n-//#include \"fpmodule.h\"\n-//#include \"fpmodule.inl\"\n-\n-//#include \n-\n-\n-FPA11* qemufpa = NULL;\n-CPUARMState* user_registers;\n-\n-/* Reset the FPA11 chip. Called to initialize and reset the emulator. */\n-void resetFPA11(void)\n-{\n- int i;\n- FPA11 *fpa11 = GET_FPA11();\n-\n- /* initialize the register type array */\n- for (i=0;i<=7;i++)\n- {\n- fpa11->fType[i] = typeNone;\n- }\n-\n- /* FPSR: set system id to FP_EMULATOR, set AC, clear all other bits */\n- fpa11->fpsr = FP_EMULATOR | BIT_AC;\n-\n- /* FPCR: set SB, AB and DA bits, clear all others */\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr = MASK_RESET;\n-#endif\n-\n- /*\n- * Real FPA11 hardware does not handle NaNs, but always takes an\n- * exception for them to be software-emulated (ARM7500FE datasheet\n- * section 10.4). There is no documented architectural requirement\n- * for NaN propagation rules and it will depend on how the OS\n- * level software emulation opted to do it. We here use prop_s_ab\n- * which matches the later VFP hardware choice and how QEMU's\n- * fpa11 emulation has worked in the past. The real Linux kernel\n- * does something slightly different: arch/arm/nwfpe/softfloat-specialize\n- * propagateFloat64NaN() has the curious behaviour that it prefers\n- * the QNaN over the SNaN, but if both are QNaN it picks A and\n- * if both are SNaN it picks B. In theory we could add this as\n- * a NaN propagation rule, but in practice FPA11 emulation is so\n- * close to totally dead that it's not worth trying to match it at\n- * this late date.\n- */\n- set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);\n- /*\n- * Use the same default NaN value as Arm VFP. This doesn't match\n- * the Linux kernel's nwfpe emulation, which uses an all-1s value.\n- */\n- set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);\n-}\n-\n-void SetRoundingMode(const unsigned int opcode)\n-{\n- int rounding_mode;\n- FPA11 *fpa11 = GET_FPA11();\n-\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr &= ~MASK_ROUNDING_MODE;\n-#endif\n- switch (opcode & MASK_ROUNDING_MODE)\n- {\n- default:\n- case ROUND_TO_NEAREST:\n- rounding_mode = float_round_nearest_even;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_TO_NEAREST;\n-#endif\n- break;\n-\n- case ROUND_TO_PLUS_INFINITY:\n- rounding_mode = float_round_up;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_TO_PLUS_INFINITY;\n-#endif\n- break;\n-\n- case ROUND_TO_MINUS_INFINITY:\n- rounding_mode = float_round_down;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_TO_MINUS_INFINITY;\n-#endif\n- break;\n-\n- case ROUND_TO_ZERO:\n- rounding_mode = float_round_to_zero;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_TO_ZERO;\n-#endif\n- break;\n- }\n- set_float_rounding_mode(rounding_mode, &fpa11->fp_status);\n-}\n-\n-void SetRoundingPrecision(const unsigned int opcode)\n-{\n- FloatX80RoundPrec rounding_precision;\n- FPA11 *fpa11 = GET_FPA11();\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr &= ~MASK_ROUNDING_PRECISION;\n-#endif\n- switch (opcode & MASK_ROUNDING_PRECISION) {\n- case ROUND_SINGLE:\n- rounding_precision = floatx80_precision_s;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_SINGLE;\n-#endif\n- break;\n-\n- case ROUND_DOUBLE:\n- rounding_precision = floatx80_precision_d;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_DOUBLE;\n-#endif\n- break;\n-\n- case ROUND_EXTENDED:\n- rounding_precision = floatx80_precision_x;\n-#ifdef MAINTAIN_FPCR\n- fpa11->fpcr |= ROUND_EXTENDED;\n-#endif\n- break;\n-\n- default:\n- rounding_precision = floatx80_precision_x;\n- break;\n- }\n- set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status);\n-}\n-\n-/* Emulate the instruction in the opcode. */\n-/* ??? This is not thread safe. */\n-unsigned int EmulateAll(unsigned int opcode, FPA11* qfpa, CPUARMState* qregs)\n-{\n- unsigned int nRc = 0;\n-// unsigned long flags;\n- FPA11 *fpa11;\n- unsigned int cp;\n-// save_flags(flags); sti();\n-\n- /* Check that this is really an FPA11 instruction: the coprocessor\n- * field in bits [11:8] must be 1 or 2.\n- */\n- cp = (opcode >> 8) & 0xf;\n- if (cp != 1 && cp != 2) {\n- return 0;\n- }\n-\n- qemufpa=qfpa;\n- user_registers=qregs;\n-\n-#if 0\n- fprintf(stderr,\"emulating FP insn 0x%08x, PC=0x%08x\\n\",\n- opcode, qregs[ARM_REG_PC]);\n-#endif\n- fpa11 = GET_FPA11();\n-\n- if (fpa11->initflag == 0)\t\t/* good place for __builtin_expect */\n- {\n- resetFPA11();\n- SetRoundingMode(ROUND_TO_NEAREST);\n- SetRoundingPrecision(ROUND_EXTENDED);\n- fpa11->initflag = 1;\n- }\n-\n- set_float_exception_flags(0, &fpa11->fp_status);\n-\n- if (TEST_OPCODE(opcode,MASK_CPRT))\n- {\n- //fprintf(stderr,\"emulating CPRT\\n\");\n- /* Emulate conversion opcodes. */\n- /* Emulate register transfer opcodes. */\n- /* Emulate comparison opcodes. */\n- nRc = EmulateCPRT(opcode);\n- }\n- else if (TEST_OPCODE(opcode,MASK_CPDO))\n- {\n- //fprintf(stderr,\"emulating CPDO\\n\");\n- /* Emulate monadic arithmetic opcodes. */\n- /* Emulate dyadic arithmetic opcodes. */\n- nRc = EmulateCPDO(opcode);\n- }\n- else if (TEST_OPCODE(opcode,MASK_CPDT))\n- {\n- //fprintf(stderr,\"emulating CPDT\\n\");\n- /* Emulate load/store opcodes. */\n- /* Emulate load/store multiple opcodes. */\n- nRc = EmulateCPDT(opcode);\n- }\n- else\n- {\n- /* Invalid instruction detected. Return FALSE. */\n- nRc = 0;\n- }\n-\n-// restore_flags(flags);\n- if(nRc == 1 && get_float_exception_flags(&fpa11->fp_status))\n- {\n- //printf(\"fef 0x%x\\n\",float_exception_flags);\n- nRc = -get_float_exception_flags(&fpa11->fp_status);\n- }\n-\n- //printf(\"returning %d\\n\",nRc);\n- return(nRc);\n-}\n-\n-#if 0\n-unsigned int EmulateAll1(unsigned int opcode)\n-{\n- switch ((opcode >> 24) & 0xf)\n- {\n- case 0xc:\n- case 0xd:\n- if ((opcode >> 20) & 0x1)\n- {\n- switch ((opcode >> 8) & 0xf)\n- {\n- case 0x1: return PerformLDF(opcode); break;\n- case 0x2: return PerformLFM(opcode); break;\n- default: return 0;\n- }\n- }\n- else\n- {\n- switch ((opcode >> 8) & 0xf)\n- {\n- case 0x1: return PerformSTF(opcode); break;\n- case 0x2: return PerformSFM(opcode); break;\n- default: return 0;\n- }\n- }\n- break;\n-\n- case 0xe:\n- if (opcode & 0x10)\n- return EmulateCPDO(opcode);\n- else\n- return EmulateCPRT(opcode);\n- break;\n-\n- default: return 0;\n- }\n-}\n-#endif\ndiff --git a/linux-user/arm/nwfpe/fpa11_cpdo.c b/linux-user/arm/nwfpe/fpa11_cpdo.c\ndeleted file mode 100644\nindex 94ac98aef5..0000000000\n--- a/linux-user/arm/nwfpe/fpa11_cpdo.c\n+++ /dev/null\n@@ -1,113 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpopcode.h\"\n-\n-unsigned int EmulateCPDO(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- unsigned int Fd, nType, nDest, nRc = 1;\n-\n- //printk(\"EmulateCPDO(0x%08x)\\n\",opcode);\n-\n- /* Get the destination size. If not valid let Linux perform\n- an invalid instruction trap. */\n- nDest = getDestinationSize(opcode);\n- if (typeNone == nDest) return 0;\n-\n- SetRoundingMode(opcode);\n-\n- /* Compare the size of the operands in Fn and Fm.\n- Choose the largest size and perform operations in that size,\n- in order to make use of all the precision of the operands.\n- If Fm is a constant, we just grab a constant of a size\n- matching the size of the operand in Fn. */\n- if (MONADIC_INSTRUCTION(opcode))\n- nType = nDest;\n- else\n- nType = fpa11->fType[getFn(opcode)];\n-\n- if (!CONSTANT_FM(opcode))\n- {\n- register unsigned int Fm = getFm(opcode);\n- if (nType < fpa11->fType[Fm])\n- {\n- nType = fpa11->fType[Fm];\n- }\n- }\n-\n- switch (nType)\n- {\n- case typeSingle : nRc = SingleCPDO(opcode); break;\n- case typeDouble : nRc = DoubleCPDO(opcode); break;\n- case typeExtended : nRc = ExtendedCPDO(opcode); break;\n- default : nRc = 0;\n- }\n-\n- /* If the operation succeeded, check to see if the result in the\n- destination register is the correct size. If not force it\n- to be. */\n- Fd = getFd(opcode);\n- nType = fpa11->fType[Fd];\n- if ((0 != nRc) && (nDest != nType))\n- {\n- switch (nDest)\n- {\n- case typeSingle:\n- {\n- if (typeDouble == nType)\n- fpa11->fpreg[Fd].fSingle =\n- float64_to_float32(fpa11->fpreg[Fd].fDouble, &fpa11->fp_status);\n- else\n- fpa11->fpreg[Fd].fSingle =\n- floatx80_to_float32(fpa11->fpreg[Fd].fExtended, &fpa11->fp_status);\n- }\n- break;\n-\n- case typeDouble:\n- {\n- if (typeSingle == nType)\n- fpa11->fpreg[Fd].fDouble =\n- float32_to_float64(fpa11->fpreg[Fd].fSingle, &fpa11->fp_status);\n- else\n- fpa11->fpreg[Fd].fDouble =\n- floatx80_to_float64(fpa11->fpreg[Fd].fExtended, &fpa11->fp_status);\n- }\n- break;\n-\n- case typeExtended:\n- {\n- if (typeSingle == nType)\n- fpa11->fpreg[Fd].fExtended =\n- float32_to_floatx80(fpa11->fpreg[Fd].fSingle, &fpa11->fp_status);\n- else\n- fpa11->fpreg[Fd].fExtended =\n- float64_to_floatx80(fpa11->fpreg[Fd].fDouble, &fpa11->fp_status);\n- }\n- break;\n- }\n-\n- fpa11->fType[Fd] = nDest;\n- }\n-\n- return nRc;\n-}\ndiff --git a/linux-user/arm/nwfpe/fpa11_cpdt.c b/linux-user/arm/nwfpe/fpa11_cpdt.c\ndeleted file mode 100644\nindex fee525937c..0000000000\n--- a/linux-user/arm/nwfpe/fpa11_cpdt.c\n+++ /dev/null\n@@ -1,382 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.com, 1998-1999\n- (c) Philip Blundell, 1998\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpu/softfloat.h\"\n-#include \"fpopcode.h\"\n-//#include \"fpmodule.h\"\n-//#include \"fpmodule.inl\"\n-\n-//#include \n-\n-static inline\n-void loadSingle(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- fpa11->fType[Fn] = typeSingle;\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(float32_val(fpa11->fpreg[Fn].fSingle), addr);\n-}\n-\n-static inline\n-void loadDouble(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- unsigned int *p;\n- p = (unsigned int*)&fpa11->fpreg[Fn].fDouble;\n- fpa11->fType[Fn] = typeDouble;\n-#if HOST_BIG_ENDIAN\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(p[0], addr); /* sign & exponent */\n- get_user_u32(p[1], addr + 4);\n-#else\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(p[0], addr + 4);\n- get_user_u32(p[1], addr); /* sign & exponent */\n-#endif\n-}\n-\n-static inline\n-void loadExtended(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- unsigned int *p;\n- p = (unsigned int*)&fpa11->fpreg[Fn].fExtended;\n- fpa11->fType[Fn] = typeExtended;\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(p[0], addr); /* sign & exponent */\n- get_user_u32(p[1], addr + 8); /* ls bits */\n- get_user_u32(p[2], addr + 4); /* ms bits */\n-}\n-\n-static inline\n-void loadMultiple(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- register unsigned int *p;\n- unsigned long x;\n-\n- p = (unsigned int*)&(fpa11->fpreg[Fn]);\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(x, addr);\n- fpa11->fType[Fn] = (x >> 14) & 0x00000003;\n-\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- case typeDouble:\n- {\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(p[0], addr + 8); /* Single */\n- get_user_u32(p[1], addr + 4); /* double msw */\n- p[2] = 0; /* empty */\n- }\n- break;\n-\n- case typeExtended:\n- {\n- /* FIXME - handle failure of get_user() */\n- get_user_u32(p[1], addr + 8);\n- get_user_u32(p[2], addr + 4); /* msw */\n- p[0] = (x & 0x80003fff);\n- }\n- break;\n- }\n-}\n-\n-static inline\n-void storeSingle(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- float32 val;\n- register unsigned int *p = (unsigned int*)&val;\n-\n- switch (fpa11->fType[Fn])\n- {\n- case typeDouble:\n- val = float64_to_float32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);\n- break;\n-\n- case typeExtended:\n- val = floatx80_to_float32(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status);\n- break;\n-\n- default: val = fpa11->fpreg[Fn].fSingle;\n- }\n-\n- /* FIXME - handle put_user() failures */\n- put_user_u32(p[0], addr);\n-}\n-\n-static inline\n-void storeDouble(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- float64 val;\n- register unsigned int *p = (unsigned int*)&val;\n-\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- val = float32_to_float64(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeExtended:\n- val = floatx80_to_float64(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status);\n- break;\n-\n- default: val = fpa11->fpreg[Fn].fDouble;\n- }\n- /* FIXME - handle put_user() failures */\n-#if HOST_BIG_ENDIAN\n- put_user_u32(p[0], addr);\t/* msw */\n- put_user_u32(p[1], addr + 4);\t/* lsw */\n-#else\n- put_user_u32(p[1], addr);\t/* msw */\n- put_user_u32(p[0], addr + 4);\t/* lsw */\n-#endif\n-}\n-\n-static inline\n-void storeExtended(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- floatx80 val;\n- register unsigned int *p = (unsigned int*)&val;\n-\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- val = float32_to_floatx80(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- val = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);\n- break;\n-\n- default: val = fpa11->fpreg[Fn].fExtended;\n- }\n-\n- /* FIXME - handle put_user() failures */\n- put_user_u32(p[0], addr); /* sign & exp */\n- put_user_u32(p[1], addr + 8);\n- put_user_u32(p[2], addr + 4); /* msw */\n-}\n-\n-static inline\n-void storeMultiple(const unsigned int Fn, target_ulong addr)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- register unsigned int nType, *p;\n-\n- p = (unsigned int*)&(fpa11->fpreg[Fn]);\n- nType = fpa11->fType[Fn];\n-\n- switch (nType)\n- {\n- case typeSingle:\n- case typeDouble:\n- {\n- put_user_u32(p[0], addr + 8); /* single */\n-\t put_user_u32(p[1], addr + 4); /* double msw */\n-\t put_user_u32(nType << 14, addr);\n- }\n- break;\n-\n- case typeExtended:\n- {\n- put_user_u32(p[2], addr + 4); /* msw */\n-\t put_user_u32(p[1], addr + 8);\n-\t put_user_u32((p[0] & 0x80003fff) | (nType << 14), addr);\n- }\n- break;\n- }\n-}\n-\n-static unsigned int PerformLDF(const unsigned int opcode)\n-{\n- target_ulong pBase, pAddress, pFinal;\n- unsigned int nRc = 1,\n- write_back = WRITE_BACK(opcode);\n-\n- //printk(\"PerformLDF(0x%08x), Fd = 0x%08x\\n\",opcode,getFd(opcode));\n-\n- pBase = readRegister(getRn(opcode));\n- if (ARM_REG_PC == getRn(opcode))\n- {\n- pBase += 8;\n- write_back = 0;\n- }\n-\n- pFinal = pBase;\n- if (BIT_UP_SET(opcode))\n- pFinal += getOffset(opcode) * 4;\n- else\n- pFinal -= getOffset(opcode) * 4;\n-\n- if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;\n-\n- switch (opcode & MASK_TRANSFER_LENGTH)\n- {\n- case TRANSFER_SINGLE : loadSingle(getFd(opcode),pAddress); break;\n- case TRANSFER_DOUBLE : loadDouble(getFd(opcode),pAddress); break;\n- case TRANSFER_EXTENDED: loadExtended(getFd(opcode),pAddress); break;\n- default: nRc = 0;\n- }\n-\n- if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);\n- return nRc;\n-}\n-\n-static unsigned int PerformSTF(const unsigned int opcode)\n-{\n- target_ulong pBase, pAddress, pFinal;\n- unsigned int nRc = 1,\n- write_back = WRITE_BACK(opcode);\n-\n- //printk(\"PerformSTF(0x%08x), Fd = 0x%08x\\n\",opcode,getFd(opcode));\n- SetRoundingMode(ROUND_TO_NEAREST);\n-\n- pBase = readRegister(getRn(opcode));\n- if (ARM_REG_PC == getRn(opcode))\n- {\n- pBase += 8;\n- write_back = 0;\n- }\n-\n- pFinal = pBase;\n- if (BIT_UP_SET(opcode))\n- pFinal += getOffset(opcode) * 4;\n- else\n- pFinal -= getOffset(opcode) * 4;\n-\n- if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;\n-\n- switch (opcode & MASK_TRANSFER_LENGTH)\n- {\n- case TRANSFER_SINGLE : storeSingle(getFd(opcode),pAddress); break;\n- case TRANSFER_DOUBLE : storeDouble(getFd(opcode),pAddress); break;\n- case TRANSFER_EXTENDED: storeExtended(getFd(opcode),pAddress); break;\n- default: nRc = 0;\n- }\n-\n- if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);\n- return nRc;\n-}\n-\n-static unsigned int PerformLFM(const unsigned int opcode)\n-{\n- unsigned int i, Fd,\n- write_back = WRITE_BACK(opcode);\n- target_ulong pBase, pAddress, pFinal;\n-\n- pBase = readRegister(getRn(opcode));\n- if (ARM_REG_PC == getRn(opcode))\n- {\n- pBase += 8;\n- write_back = 0;\n- }\n-\n- pFinal = pBase;\n- if (BIT_UP_SET(opcode))\n- pFinal += getOffset(opcode) * 4;\n- else\n- pFinal -= getOffset(opcode) * 4;\n-\n- if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;\n-\n- Fd = getFd(opcode);\n- for (i=getRegisterCount(opcode);i>0;i--)\n- {\n- loadMultiple(Fd,pAddress);\n- pAddress += 12; Fd++;\n- if (Fd == 8) Fd = 0;\n- }\n-\n- if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);\n- return 1;\n-}\n-\n-static unsigned int PerformSFM(const unsigned int opcode)\n-{\n- unsigned int i, Fd,\n- write_back = WRITE_BACK(opcode);\n- target_ulong pBase, pAddress, pFinal;\n-\n- pBase = readRegister(getRn(opcode));\n- if (ARM_REG_PC == getRn(opcode))\n- {\n- pBase += 8;\n- write_back = 0;\n- }\n-\n- pFinal = pBase;\n- if (BIT_UP_SET(opcode))\n- pFinal += getOffset(opcode) * 4;\n- else\n- pFinal -= getOffset(opcode) * 4;\n-\n- if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;\n-\n- Fd = getFd(opcode);\n- for (i=getRegisterCount(opcode);i>0;i--)\n- {\n- storeMultiple(Fd,pAddress);\n- pAddress += 12; Fd++;\n- if (Fd == 8) Fd = 0;\n- }\n-\n- if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);\n- return 1;\n-}\n-\n-#if 1\n-unsigned int EmulateCPDT(const unsigned int opcode)\n-{\n- unsigned int nRc = 0;\n-\n- //printk(\"EmulateCPDT(0x%08x)\\n\",opcode);\n-\n- if (LDF_OP(opcode))\n- {\n- nRc = PerformLDF(opcode);\n- }\n- else if (LFM_OP(opcode))\n- {\n- nRc = PerformLFM(opcode);\n- }\n- else if (STF_OP(opcode))\n- {\n- nRc = PerformSTF(opcode);\n- }\n- else if (SFM_OP(opcode))\n- {\n- nRc = PerformSFM(opcode);\n- }\n- else\n- {\n- nRc = 0;\n- }\n-\n- return nRc;\n-}\n-#endif\ndiff --git a/linux-user/arm/nwfpe/fpa11_cprt.c b/linux-user/arm/nwfpe/fpa11_cprt.c\ndeleted file mode 100644\nindex 04dc2ebb02..0000000000\n--- a/linux-user/arm/nwfpe/fpa11_cprt.c\n+++ /dev/null\n@@ -1,284 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n- (c) Philip Blundell, 1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpu/softfloat.h\"\n-#include \"fpopcode.h\"\n-#include \"fpa11.inl\"\n-//#include \"fpmodule.h\"\n-//#include \"fpmodule.inl\"\n-\n-unsigned int PerformFLT(const unsigned int opcode);\n-unsigned int PerformFIX(const unsigned int opcode);\n-\n-static unsigned int\n-PerformComparison(const unsigned int opcode);\n-\n-unsigned int EmulateCPRT(const unsigned int opcode)\n-{\n- unsigned int nRc = 1;\n-\n- //printk(\"EmulateCPRT(0x%08x)\\n\",opcode);\n-\n- if (opcode & 0x800000)\n- {\n- /* This is some variant of a comparison (PerformComparison will\n-\tsort out which one). Since most of the other CPRT\n-\tinstructions are oddball cases of some sort or other it makes\n-\tsense to pull this out into a fast path. */\n- return PerformComparison(opcode);\n- }\n-\n- /* Hint to GCC that we'd like a jump table rather than a load of CMPs */\n- switch ((opcode & 0x700000) >> 20)\n- {\n- case FLT_CODE >> 20: nRc = PerformFLT(opcode); break;\n- case FIX_CODE >> 20: nRc = PerformFIX(opcode); break;\n-\n- case WFS_CODE >> 20: writeFPSR(readRegister(getRd(opcode))); break;\n- case RFS_CODE >> 20: writeRegister(getRd(opcode),readFPSR()); break;\n-\n-#if 0 /* We currently have no use for the FPCR, so there's no point\n-\t in emulating it. */\n- case WFC_CODE >> 20: writeFPCR(readRegister(getRd(opcode)));\n- case RFC_CODE >> 20: writeRegister(getRd(opcode),readFPCR()); break;\n-#endif\n-\n- default: nRc = 0;\n- }\n-\n- return nRc;\n-}\n-\n-unsigned int PerformFLT(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n-\n- unsigned int nRc = 1;\n- SetRoundingMode(opcode);\n-\n- switch (opcode & MASK_ROUNDING_PRECISION)\n- {\n- case ROUND_SINGLE:\n- {\n- fpa11->fType[getFn(opcode)] = typeSingle;\n- fpa11->fpreg[getFn(opcode)].fSingle =\n-\t int32_to_float32(readRegister(getRd(opcode)), &fpa11->fp_status);\n- }\n- break;\n-\n- case ROUND_DOUBLE:\n- {\n- fpa11->fType[getFn(opcode)] = typeDouble;\n- fpa11->fpreg[getFn(opcode)].fDouble =\n- int32_to_float64(readRegister(getRd(opcode)), &fpa11->fp_status);\n- }\n- break;\n-\n- case ROUND_EXTENDED:\n- {\n- fpa11->fType[getFn(opcode)] = typeExtended;\n- fpa11->fpreg[getFn(opcode)].fExtended =\n-\t int32_to_floatx80(readRegister(getRd(opcode)), &fpa11->fp_status);\n- }\n- break;\n-\n- default: nRc = 0;\n- }\n-\n- return nRc;\n-}\n-\n-unsigned int PerformFIX(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- unsigned int nRc = 1;\n- unsigned int Fn = getFm(opcode);\n-\n- SetRoundingMode(opcode);\n-\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- {\n- writeRegister(getRd(opcode),\n-\t float32_to_int32(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status));\n- }\n- break;\n-\n- case typeDouble:\n- {\n- //printf(\"F%d is 0x%\" PRIx64 \"\\n\",Fn,fpa11->fpreg[Fn].fDouble);\n- writeRegister(getRd(opcode),\n-\t float64_to_int32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status));\n- }\n- break;\n-\n- case typeExtended:\n- {\n- writeRegister(getRd(opcode),\n-\t floatx80_to_int32(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status));\n- }\n- break;\n-\n- default: nRc = 0;\n- }\n-\n- return nRc;\n-}\n-\n-\n-static __inline unsigned int\n-PerformComparisonOperation(floatx80 Fn, floatx80 Fm)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- unsigned int flags = 0;\n-\n- /* test for less than condition */\n- if (floatx80_lt(Fn,Fm, &fpa11->fp_status))\n- {\n- flags |= CC_NEGATIVE;\n- }\n-\n- /* test for equal condition */\n- if (floatx80_eq_quiet(Fn,Fm, &fpa11->fp_status))\n- {\n- flags |= CC_ZERO;\n- }\n-\n- /* test for greater than or equal condition */\n- if (floatx80_lt(Fm,Fn, &fpa11->fp_status))\n- {\n- flags |= CC_CARRY;\n- }\n-\n- writeConditionCodes(flags);\n- return 1;\n-}\n-\n-/* This instruction sets the flags N, Z, C, V in the FPSR. */\n-\n-static unsigned int PerformComparison(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- unsigned int Fn, Fm;\n- floatx80 rFn, rFm;\n- int e_flag = opcode & 0x400000;\t/* 1 if CxFE */\n- int n_flag = opcode & 0x200000;\t/* 1 if CNxx */\n- unsigned int flags = 0;\n-\n- //printk(\"PerformComparison(0x%08x)\\n\",opcode);\n-\n- Fn = getFn(opcode);\n- Fm = getFm(opcode);\n-\n- /* Check for unordered condition and convert all operands to 80-bit\n- format.\n- ?? Might be some mileage in avoiding this conversion if possible.\n- Eg, if both operands are 32-bit, detect this and do a 32-bit\n- comparison (cheaper than an 80-bit one). */\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- //printk(\"single.\\n\");\n-\tif (float32_is_any_nan(fpa11->fpreg[Fn].fSingle))\n-\t goto unordered;\n- rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- //printk(\"double.\\n\");\n-\tif (float64_is_any_nan(fpa11->fpreg[Fn].fDouble))\n-\t goto unordered;\n- rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);\n- break;\n-\n- case typeExtended:\n- //printk(\"extended.\\n\");\n-\tif (floatx80_is_any_nan(fpa11->fpreg[Fn].fExtended))\n-\t goto unordered;\n- rFn = fpa11->fpreg[Fn].fExtended;\n- break;\n-\n- default: return 0;\n- }\n-\n- if (CONSTANT_FM(opcode))\n- {\n- //printk(\"Fm is a constant: #%d.\\n\",Fm);\n- rFm = getExtendedConstant(Fm);\n- if (floatx80_is_any_nan(rFm))\n- goto unordered;\n- }\n- else\n- {\n- //printk(\"Fm = r%d which contains a \",Fm);\n- switch (fpa11->fType[Fm])\n- {\n- case typeSingle:\n- //printk(\"single.\\n\");\n-\t if (float32_is_any_nan(fpa11->fpreg[Fm].fSingle))\n-\t goto unordered;\n- rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle, &fpa11->fp_status);\n- break;\n-\n- case typeDouble:\n- //printk(\"double.\\n\");\n-\t if (float64_is_any_nan(fpa11->fpreg[Fm].fDouble))\n-\t goto unordered;\n- rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble, &fpa11->fp_status);\n- break;\n-\n- case typeExtended:\n- //printk(\"extended.\\n\");\n-\t if (floatx80_is_any_nan(fpa11->fpreg[Fm].fExtended))\n-\t goto unordered;\n- rFm = fpa11->fpreg[Fm].fExtended;\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- if (n_flag)\n- {\n- rFm.high ^= 0x8000;\n- }\n-\n- return PerformComparisonOperation(rFn,rFm);\n-\n- unordered:\n- /* ?? The FPA data sheet is pretty vague about this, in particular\n- about whether the non-E comparisons can ever raise exceptions.\n- This implementation is based on a combination of what it says in\n- the data sheet, observation of how the Acorn emulator actually\n- behaves (and how programs expect it to) and guesswork. */\n- flags |= CC_OVERFLOW;\n- flags &= ~(CC_ZERO | CC_NEGATIVE);\n-\n- if (BIT_AC & readFPSR()) flags |= CC_CARRY;\n-\n- if (e_flag) float_raise(float_flag_invalid, &fpa11->fp_status);\n-\n- writeConditionCodes(flags);\n- return 1;\n-}\ndiff --git a/linux-user/arm/nwfpe/fpopcode.c b/linux-user/arm/nwfpe/fpopcode.c\ndeleted file mode 100644\nindex 6784256d28..0000000000\n--- a/linux-user/arm/nwfpe/fpopcode.c\n+++ /dev/null\n@@ -1,91 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpu/softfloat.h\"\n-#include \"fpopcode.h\"\n-#include \"fpsr.h\"\n-//#include \"fpmodule.h\"\n-//#include \"fpmodule.inl\"\n-\n-const floatx80 floatx80Constant[] = {\n- { 0x0000000000000000ULL, 0x0000},\t/* extended 0.0 */\n- { 0x8000000000000000ULL, 0x3fff},\t/* extended 1.0 */\n- { 0x8000000000000000ULL, 0x4000},\t/* extended 2.0 */\n- { 0xc000000000000000ULL, 0x4000},\t/* extended 3.0 */\n- { 0x8000000000000000ULL, 0x4001},\t/* extended 4.0 */\n- { 0xa000000000000000ULL, 0x4001},\t/* extended 5.0 */\n- { 0x8000000000000000ULL, 0x3ffe},\t/* extended 0.5 */\n- { 0xa000000000000000ULL, 0x4002}\t/* extended 10.0 */\n-};\n-\n-const float64 float64Constant[] = {\n- const_float64(0x0000000000000000ULL),\t\t/* double 0.0 */\n- const_float64(0x3ff0000000000000ULL),\t\t/* double 1.0 */\n- const_float64(0x4000000000000000ULL),\t\t/* double 2.0 */\n- const_float64(0x4008000000000000ULL),\t\t/* double 3.0 */\n- const_float64(0x4010000000000000ULL),\t\t/* double 4.0 */\n- const_float64(0x4014000000000000ULL),\t\t/* double 5.0 */\n- const_float64(0x3fe0000000000000ULL),\t\t/* double 0.5 */\n- const_float64(0x4024000000000000ULL)\t\t\t/* double 10.0 */\n-};\n-\n-const float32 float32Constant[] = {\n- const_float32(0x00000000),\t\t\t\t/* single 0.0 */\n- const_float32(0x3f800000),\t\t\t\t/* single 1.0 */\n- const_float32(0x40000000),\t\t\t\t/* single 2.0 */\n- const_float32(0x40400000),\t\t\t\t/* single 3.0 */\n- const_float32(0x40800000),\t\t\t\t/* single 4.0 */\n- const_float32(0x40a00000),\t\t\t\t/* single 5.0 */\n- const_float32(0x3f000000),\t\t\t\t/* single 0.5 */\n- const_float32(0x41200000)\t\t\t\t/* single 10.0 */\n-};\n-\n-unsigned int getRegisterCount(const unsigned int opcode)\n-{\n- unsigned int nRc;\n-\n- switch (opcode & MASK_REGISTER_COUNT)\n- {\n- case 0x00000000: nRc = 4; break;\n- case 0x00008000: nRc = 1; break;\n- case 0x00400000: nRc = 2; break;\n- case 0x00408000: nRc = 3; break;\n- default: nRc = 0;\n- }\n-\n- return(nRc);\n-}\n-\n-unsigned int getDestinationSize(const unsigned int opcode)\n-{\n- unsigned int nRc;\n-\n- switch (opcode & MASK_DESTINATION_SIZE)\n- {\n- case 0x00000000: nRc = typeSingle; break;\n- case 0x00000080: nRc = typeDouble; break;\n- case 0x00080000: nRc = typeExtended; break;\n- default: nRc = typeNone;\n- }\n-\n- return(nRc);\n-}\ndiff --git a/linux-user/arm/nwfpe/single_cpdo.c b/linux-user/arm/nwfpe/single_cpdo.c\ndeleted file mode 100644\nindex 21e177baeb..0000000000\n--- a/linux-user/arm/nwfpe/single_cpdo.c\n+++ /dev/null\n@@ -1,253 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"qemu/osdep.h\"\n-#include \"fpa11.h\"\n-#include \"fpu/softfloat.h\"\n-#include \"fpopcode.h\"\n-\n-float32 float32_exp(float32 Fm);\n-float32 float32_ln(float32 Fm);\n-float32 float32_sin(float32 rFm);\n-float32 float32_cos(float32 rFm);\n-float32 float32_arcsin(float32 rFm);\n-float32 float32_arctan(float32 rFm);\n-float32 float32_log(float32 rFm);\n-float32 float32_tan(float32 rFm);\n-float32 float32_arccos(float32 rFm);\n-float32 float32_pow(float32 rFn,float32 rFm);\n-float32 float32_pol(float32 rFn,float32 rFm);\n-\n-unsigned int SingleCPDO(const unsigned int opcode)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- float32 rFm, rFn = float32_zero;\n- unsigned int Fd, Fm, Fn, nRc = 1;\n-\n- Fm = getFm(opcode);\n- if (CONSTANT_FM(opcode))\n- {\n- rFm = getSingleConstant(Fm);\n- }\n- else\n- {\n- switch (fpa11->fType[Fm])\n- {\n- case typeSingle:\n- rFm = fpa11->fpreg[Fm].fSingle;\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- if (!MONADIC_INSTRUCTION(opcode))\n- {\n- Fn = getFn(opcode);\n- switch (fpa11->fType[Fn])\n- {\n- case typeSingle:\n- rFn = fpa11->fpreg[Fn].fSingle;\n- break;\n-\n- default: return 0;\n- }\n- }\n-\n- Fd = getFd(opcode);\n- switch (opcode & MASK_ARITHMETIC_OPCODE)\n- {\n- /* dyadic opcodes */\n- case ADF_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_add(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case MUF_CODE:\n- case FML_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_mul(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case SUF_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_sub(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case RSF_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_sub(rFm,rFn, &fpa11->fp_status);\n- break;\n-\n- case DVF_CODE:\n- case FDV_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_div(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n- case RDF_CODE:\n- case FRD_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_div(rFm,rFn, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case POW_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_pow(rFn,rFm);\n- break;\n-\n- case RPW_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_pow(rFm,rFn);\n- break;\n-#endif\n-\n- case RMF_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_rem(rFn,rFm, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case POL_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_pol(rFn,rFm);\n- break;\n-#endif\n-\n- /* monadic opcodes */\n- case MVF_CODE:\n- fpa11->fpreg[Fd].fSingle = rFm;\n- break;\n-\n- case MNF_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_chs(rFm);\n- break;\n-\n- case ABS_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_abs(rFm);\n- break;\n-\n- case RND_CODE:\n- case URD_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm, &fpa11->fp_status);\n- break;\n-\n- case SQT_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_sqrt(rFm, &fpa11->fp_status);\n- break;\n-\n-#if 0\n- case LOG_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_log(rFm);\n- break;\n-\n- case LGN_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_ln(rFm);\n- break;\n-\n- case EXP_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_exp(rFm);\n- break;\n-\n- case SIN_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_sin(rFm);\n- break;\n-\n- case COS_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_cos(rFm);\n- break;\n-\n- case TAN_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_tan(rFm);\n- break;\n-\n- case ASN_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_arcsin(rFm);\n- break;\n-\n- case ACS_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_arccos(rFm);\n- break;\n-\n- case ATN_CODE:\n- fpa11->fpreg[Fd].fSingle = float32_arctan(rFm);\n- break;\n-#endif\n-\n- case NRM_CODE:\n- break;\n-\n- default:\n- {\n- nRc = 0;\n- }\n- }\n-\n- if (0 != nRc) fpa11->fType[Fd] = typeSingle;\n- return nRc;\n-}\n-\n-#if 0\n-float32 float32_exp(float32 Fm)\n-{\n-//series\n-}\n-\n-float32 float32_ln(float32 Fm)\n-{\n-//series\n-}\n-\n-float32 float32_sin(float32 rFm)\n-{\n-//series\n-}\n-\n-float32 float32_cos(float32 rFm)\n-{\n-//series\n-}\n-\n-float32 float32_arcsin(float32 rFm)\n-{\n-//series\n-}\n-\n-float32 float32_arctan(float32 rFm)\n-{\n- //series\n-}\n-\n-float32 float32_arccos(float32 rFm)\n-{\n- //return float32_sub(halfPi,float32_arcsin(rFm));\n-}\n-\n-float32 float32_log(float32 rFm)\n-{\n- return float32_div(float32_ln(rFm),getSingleConstant(7));\n-}\n-\n-float32 float32_tan(float32 rFm)\n-{\n- return float32_div(float32_sin(rFm),float32_cos(rFm));\n-}\n-\n-float32 float32_pow(float32 rFn,float32 rFm)\n-{\n- return float32_exp(float32_mul(rFm,float32_ln(rFn)));\n-}\n-\n-float32 float32_pol(float32 rFn,float32 rFm)\n-{\n- return float32_arctan(float32_div(rFn,rFm));\n-}\n-#endif\ndiff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build\nindex 348ffb810d..4f35536c13 100644\n--- a/linux-user/arm/meson.build\n+++ b/linux-user/arm/meson.build\n@@ -1,5 +1,3 @@\n-subdir('nwfpe')\n-\n syscall_nr_generators += {\n 'arm': generator(sh,\n arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],\ndiff --git a/linux-user/arm/nwfpe/fpa11.inl b/linux-user/arm/nwfpe/fpa11.inl\ndeleted file mode 100644\nindex 6c6f380d4d..0000000000\n--- a/linux-user/arm/nwfpe/fpa11.inl\n+++ /dev/null\n@@ -1,50 +0,0 @@\n-/*\n- NetWinder Floating Point Emulator\n- (c) Rebel.COM, 1998,1999\n-\n- Direct questions, comments to Scott Bambrough \n-\n- This program is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n- the Free Software Foundation; either version 2 of the License, or\n- (at your option) any later version.\n-\n- This program is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- GNU General Public License for more details.\n-\n- You should have received a copy of the GNU General Public License\n- along with this program; if not, see .\n-*/\n-\n-#include \"fpa11.h\"\n-\n-/* Read and write floating point status register */\n-static inline unsigned int readFPSR(void)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- return(fpa11->fpsr);\n-}\n-\n-static inline void writeFPSR(FPSR reg)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- /* the sysid byte in the status register is readonly */\n- fpa11->fpsr = (fpa11->fpsr & MASK_SYSID) | (reg & ~MASK_SYSID);\n-}\n-\n-/* Read and write floating point control register */\n-static inline FPCR readFPCR(void)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- /* clear SB, AB and DA bits before returning FPCR */\n- return(fpa11->fpcr & ~MASK_RFC);\n-}\n-\n-static inline void writeFPCR(FPCR reg)\n-{\n- FPA11 *fpa11 = GET_FPA11();\n- fpa11->fpcr &= ~MASK_WFC;\t\t/* clear SB, AB and DA bits */\n- fpa11->fpcr |= (reg & MASK_WFC);\t/* write SB, AB and DA bits */\n-}\ndiff --git a/linux-user/arm/nwfpe/meson.build b/linux-user/arm/nwfpe/meson.build\ndeleted file mode 100644\nindex 1c27e55f2a..0000000000\n--- a/linux-user/arm/nwfpe/meson.build\n+++ /dev/null\n@@ -1,10 +0,0 @@\n-linux_user_ss.add(when: 'TARGET_ARM', if_true: files(\n- 'double_cpdo.c',\n- 'extended_cpdo.c',\n- 'fpa11.c',\n- 'fpa11_cpdo.c',\n- 'fpa11_cpdt.c',\n- 'fpa11_cprt.c',\n- 'fpopcode.c',\n- 'single_cpdo.c',\n-))\n","prefixes":["for-11.1"]}