{"id":2222484,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2222484/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260412101731.107059-1-xry111@xry111.site/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260412101731.107059-1-xry111@xry111.site>","list_archive_url":null,"date":"2026-04-12T10:17:31","name":"[v8] PCI: loongson: Override PCIe bridge supported speeds for Loongson-3C6000 series","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e10df388fe41c9358887994e261f3fffa10db042","submitter":{"id":84026,"url":"http://patchwork.ozlabs.org/api/1.2/people/84026/?format=json","name":"Xi Ruoyao","email":"xry111@xry111.site"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260412101731.107059-1-xry111@xry111.site/mbox/","series":[{"id":499593,"url":"http://patchwork.ozlabs.org/api/1.2/series/499593/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499593","date":"2026-04-12T10:17:31","name":"[v8] PCI: loongson: Override PCIe bridge supported speeds for Loongson-3C6000 series","version":8,"mbox":"http://patchwork.ozlabs.org/series/499593/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222484/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222484/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=xry111.site header.i=@xry111.site header.a=rsa-sha256\n header.s=default header.b=bj31Cg2g;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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We hope this patch can prevent\nsimilar problems in future driver changes (similar checks may be\nimplemented in other GPU, storage controller, NIC, etc. drivers).\n\nManually override the `supported_speeds` field for affected PCIe bridges\nwith those found on the upstream bus to correctly reflect the supported\nlink speeds.\n\nThis patch was originally found from AOSC OS[1].\n\nLink: https://github.com/AOSC-Tracking/linux/pull/2 #1\nTested-by: Lain Fearyncess Yang \nTested-by: Ayden Meng \nSigned-off-by: Ayden Meng \nSigned-off-by: Mingcong Bai \nLink: https://github.com/AOSC-Tracking/linux/commit/4392f441363abdf6fa0a0433d73175a17f493454\n[Ziyao Li: move from drivers/pci/quirks.c to drivers/pci/controller/pci-loongson.c]\nSigned-off-by: Ziyao Li \nTested-by: Mingcong Bai \nReviewed-by: Huacai Chen \n[Xi Ruoyao: Fix falling through logic and add kernel log output;\n add Fixes tag and rebase to 7.0-rc7]\nCc: stable@vger.kernel.org\nFixes: cd89edda4002 (\"PCI: loongson: Add ACPI init support\")\nSigned-off-by: Xi Ruoyao \n---\n\nChanges in v8:\n- Add the Fixes tag.\n- Link to v7: https://lore.kernel.org/all/20260121-loongson-pci1-v7-1-fc79c85a574d@uniontech.com/\n\nZiyao Li's original commentary message follows below:\n\nThe reason of not just copying pdev->bus->self->supported_speeds is\nthat we're concerned that this approach assumes the upstream port\nreports the same capabilities as bridge, which may not always be the\ncase in future silicon revisions.\n\nOur current conservative approach ensures we only enable speeds that\nare physically supported by checking the actual max_bus_speed. For\nexample, if there's a future Loongson-3C9999 where the virtual bridge\nreports Gen4 support but the physical bridge only supports Gen3.\n\nIn this scenario, directly copying the upstream port's supported_speeds\nwould incorrectly report Gen4 support for the downstream bridge. The\ncurrent patch ensures we only set speed bits up to what the hardware\nactually supports, based on the measured max_bus_speed. This seems\nsafer for future silicon.\n\nChanges in v7:\n- adjust commit message\n- Link to v6: https://lore.kernel.org/r/20260114-loongson-pci1-v6-1-ee8a18f5d242@uniontech.com\n\nChanges in v6:\n- adjust commit message\n- Link to v5: https://lore.kernel.org/r/20260113-loongson-pci1-v5-1-264c9b4a90ab@uniontech.com\n\nChanges in v5:\n- style adjust\n- Link to v4: https://lore.kernel.org/r/20260113-loongson-pci1-v4-1-1921d6479fe4@uniontech.com\n\nChanges in v4:\n- rename subject\n- use 0x3c19/0x3c29 instead of 3c19/3c29\n- Link to v3: https://lore.kernel.org/r/20260109-loongson-pci1-v3-1-5ddc5ae3ba93@uniontech.com\n\nChanges in v3:\n- Adjust commit message\n- Make the program flow more intuitive\n- Link to v2: https://lore.kernel.org/r/20260104-loongson-pci1-v2-1-d151e57b6ef8@uniontech.com\n\nChanges in v2:\n- Link to v1: https://lore.kernel.org/r/20250822-loongson-pci1-v1-1-39aabbd11fbd@uniontech.com\n- Move from arch/loongarch/pci/pci.c to drivers/pci/controller/pci-loongson.c\n- Fix falling through logic and add kernel log output by Xi Ruoyao\n\n drivers/pci/controller/pci-loongson.c | 36 +++++++++++++++++++++++++++\n 1 file changed, 36 insertions(+)","diff":"diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c\nindex bc630ab8a283..a4250d7af1bf 100644\n--- a/drivers/pci/controller/pci-loongson.c\n+++ b/drivers/pci/controller/pci-loongson.c\n@@ -176,6 +176,42 @@ static void loongson_pci_msi_quirk(struct pci_dev *dev)\n }\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT5, loongson_pci_msi_quirk);\n \n+/*\n+ * Older steppings of the Loongson-3C6000 series incorrectly report the\n+ * supported link speeds on their PCIe bridges (device IDs 0x3c19,\n+ * 0x3c29) as only 2.5 GT/s, despite the upstream bus supporting speeds\n+ * from 2.5 GT/s up to 16 GT/s.\n+ */\n+static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev)\n+{\n+\tu8 old_supported_speeds = pdev->supported_speeds;\n+\n+\tswitch (pdev->bus->max_bus_speed) {\n+\tcase PCIE_SPEED_16_0GT:\n+\t\tpdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB;\n+\t\tfallthrough;\n+\tcase PCIE_SPEED_8_0GT:\n+\t\tpdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB;\n+\t\tfallthrough;\n+\tcase PCIE_SPEED_5_0GT:\n+\t\tpdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;\n+\t\tfallthrough;\n+\tcase PCIE_SPEED_2_5GT:\n+\t\tpdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB;\n+\t\tbreak;\n+\tdefault:\n+\t\tpci_warn(pdev, \"unexpected max bus speed\");\n+\n+\t\treturn;\n+\t}\n+\n+\tif (pdev->supported_speeds != old_supported_speeds)\n+\t\tpci_info(pdev, \"fixing up supported link speeds: 0x%x => 0x%x\",\n+\t\t\t old_supported_speeds, pdev->supported_speeds);\n+}\n+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk);\n+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk);\n+\n static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)\n {\n \tstruct pci_config_window *cfg;\n","prefixes":["v8"]}