{"id":2222471,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2222471/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/f257db26a7123c201917bf657d1d147e7cc63965.1775959096.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-12T02:20:22","name":"[v6,5/7] target/riscv: add sdext enter Debug Mode on ebreak","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4af35932f0a1c4ece87c3baf3874b1fa892aa12c","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/f257db26a7123c201917bf657d1d147e7cc63965.1775959096.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":499584,"url":"http://patchwork.ozlabs.org/api/1.2/series/499584/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584","date":"2026-04-12T02:20:20","name":"riscv: add initial sdext support","version":6,"mbox":"http://patchwork.ozlabs.org/series/499584/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222471/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222471/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=AcVIGl+C;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf43.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nRoute EBREAK via helper_sdext_ebreak. If Sdext is enabled and the\nmatching dcsr.ebreak* bit is set, enter Debug Mode with cause=ebreak\nand stop with EXCP_DEBUG. Otherwise keep the normal breakpoint trap.\n\nSigned-off-by: Chao Liu \nReviewed-by: Daniel Henrique Barboza \nTested-by: Tao Tang \n---\n target/riscv/helper.h | 1 +\n .../riscv/insn_trans/trans_privileged.c.inc | 6 ++++\n target/riscv/op_helper.c | 34 +++++++++++++++++++\n 3 files changed, 41 insertions(+)","diff":"diff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex c8e76eb116..9538e816f0 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -143,6 +143,7 @@ DEF_HELPER_1(tlb_flush_all, void, env)\n DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl)\n /* Native Debug */\n DEF_HELPER_1(itrigger_match, void, env)\n+DEF_HELPER_2(sdext_ebreak, void, env, tl)\n #endif\n \n /* Hypervisor functions */\ndiff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc\nindex f8641b1977..84f0c77513 100644\n--- a/target/riscv/insn_trans/trans_privileged.c.inc\n+++ b/target/riscv/insn_trans/trans_privileged.c.inc\n@@ -68,9 +68,15 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)\n if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {\n generate_exception(ctx, RISCV_EXCP_SEMIHOST);\n } else {\n+#ifndef CONFIG_USER_ONLY\n+ gen_update_pc(ctx, 0);\n+ gen_helper_sdext_ebreak(tcg_env, tcg_constant_tl(ebreak_addr));\n+ ctx->base.is_jmp = DISAS_NORETURN;\n+#else\n tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,\n offsetof(CPURISCVState, badaddr));\n generate_exception(ctx, RISCV_EXCP_BREAKPOINT);\n+#endif\n }\n return true;\n }\ndiff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\nindex ce68ee5959..58d47b88c1 100644\n--- a/target/riscv/op_helper.c\n+++ b/target/riscv/op_helper.c\n@@ -456,6 +456,40 @@ target_ulong helper_dret(CPURISCVState *env)\n #endif\n }\n \n+void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc)\n+{\n+ CPUState *cs = env_cpu(env);\n+ bool enter_debug = false;\n+\n+ if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode) {\n+ if (env->virt_enabled) {\n+ if (env->priv == PRV_S) {\n+ enter_debug = env->dcsr & DCSR_EBREAKVS;\n+ } else if (env->priv == PRV_U) {\n+ enter_debug = env->dcsr & DCSR_EBREAKVU;\n+ }\n+ } else {\n+ if (env->priv == PRV_M) {\n+ enter_debug = env->dcsr & DCSR_EBREAKM;\n+ } else if (env->priv == PRV_S) {\n+ enter_debug = env->dcsr & DCSR_EBREAKS;\n+ } else if (env->priv == PRV_U) {\n+ enter_debug = env->dcsr & DCSR_EBREAKU;\n+ }\n+ }\n+ }\n+\n+ env->badaddr = pc;\n+\n+ if (enter_debug) {\n+ riscv_cpu_enter_debug_mode(env, pc, DCSR_CAUSE_EBREAK);\n+ cs->exception_index = EXCP_DEBUG;\n+ cpu_loop_exit_restore(cs, GETPC());\n+ }\n+\n+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC());\n+}\n+\n target_ulong helper_mnret(CPURISCVState *env)\n {\n target_ulong retpc = env->mnepc;\n","prefixes":["v6","5/7"]}