{"id":2222469,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2222469/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/279d8e6c4bb55ae831f929c105a20c3372de636b.1775959096.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<279d8e6c4bb55ae831f929c105a20c3372de636b.1775959096.git.chao.liu.zevorn@gmail.com>","list_archive_url":null,"date":"2026-04-12T02:20:21","name":"[v6,4/7] target/riscv: add dret instruction","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f292ebe46716ef95b90bb8de84133d6fd298ee88","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/279d8e6c4bb55ae831f929c105a20c3372de636b.1775959096.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":499584,"url":"http://patchwork.ozlabs.org/api/1.2/series/499584/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584","date":"2026-04-12T02:20:20","name":"riscv: add initial sdext support","version":6,"mbox":"http://patchwork.ozlabs.org/series/499584/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222469/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222469/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Z9QXLuY0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf43.google.com","X-Spam_score_int":"-10","X-Spam_score":"-1.1","X-Spam_bar":"-","X-Spam_report":"(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1,\n FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nAdd DRET decode/translate and a helper to leave Debug Mode and return\nto dpc. Executing DRET outside Debug Mode raises illegal instruction.\n\nSigned-off-by: Chao Liu \nReviewed-by: Daniel Henrique Barboza \nTested-by: Tao Tang \n---\n target/riscv/helper.h | 1 +\n target/riscv/insn32.decode | 1 +\n target/riscv/insn_trans/trans_privileged.c.inc | 18 ++++++++++++++++++\n target/riscv/op_helper.c | 16 ++++++++++++++++\n 4 files changed, 36 insertions(+)","diff":"diff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex 54d2331966..c8e76eb116 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -133,6 +133,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)\n #ifndef CONFIG_USER_ONLY\n DEF_HELPER_1(sret, tl, env)\n DEF_HELPER_1(mret, tl, env)\n+DEF_HELPER_1(dret, tl, env)\n DEF_HELPER_1(mnret, tl, env)\n DEF_HELPER_1(ctr_clear, void, env)\n DEF_HELPER_1(wfi, void, env)\ndiff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\nindex 6e35c4b1e6..4db842d5d9 100644\n--- a/target/riscv/insn32.decode\n+++ b/target/riscv/insn32.decode\n@@ -118,6 +118,7 @@ sctrclr 000100000100 00000 000 00000 1110011\n uret 0000000 00010 00000 000 00000 1110011\n sret 0001000 00010 00000 000 00000 1110011\n mret 0011000 00010 00000 000 00000 1110011\n+dret 0111101 10010 00000 000 00000 1110011\n wfi 0001000 00101 00000 000 00000 1110011\n sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma\n \ndiff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc\nindex 8a62b4cfcd..f8641b1977 100644\n--- a/target/riscv/insn_trans/trans_privileged.c.inc\n+++ b/target/riscv/insn_trans/trans_privileged.c.inc\n@@ -125,6 +125,24 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)\n #endif\n }\n \n+static bool trans_dret(DisasContext *ctx, arg_dret *a)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ if (!ctx->cfg_ptr->ext_sdext) {\n+ return false;\n+ }\n+ decode_save_opc(ctx, 0);\n+ translator_io_start(&ctx->base);\n+ gen_update_pc(ctx, 0);\n+ gen_helper_dret(cpu_pc, tcg_env);\n+ exit_tb(ctx); /* no chaining */\n+ ctx->base.is_jmp = DISAS_NORETURN;\n+ return true;\n+#else\n+ return false;\n+#endif\n+}\n+\n static bool trans_mnret(DisasContext *ctx, arg_mnret *a)\n {\n #ifndef CONFIG_USER_ONLY\ndiff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\nindex dde40a5549..ce68ee5959 100644\n--- a/target/riscv/op_helper.c\n+++ b/target/riscv/op_helper.c\n@@ -440,6 +440,22 @@ target_ulong helper_mret(CPURISCVState *env)\n return retpc;\n }\n \n+target_ulong helper_dret(CPURISCVState *env)\n+{\n+ uintptr_t ra = GETPC();\n+#ifdef CONFIG_USER_ONLY\n+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);\n+ return 0;\n+#else\n+ if (!riscv_cpu_cfg(env)->ext_sdext || !env->debug_mode) {\n+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);\n+ }\n+ target_ulong retpc = env->dpc & get_xepc_mask(env);\n+ riscv_cpu_leave_debug_mode(env);\n+ return retpc;\n+#endif\n+}\n+\n target_ulong helper_mnret(CPURISCVState *env)\n {\n target_ulong retpc = env->mnepc;\n","prefixes":["v6","4/7"]}