{"id":2221636,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221636/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410023055.2439146-10-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410023055.2439146-10-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-10T02:30:52","name":"[V12,09/12] arm64: dts: imx8mp: Add Root Port node and PERST property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b1a6f411f80cfaaf191c956e56c1641e0cc4f6a0","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/1.2/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410023055.2439146-10-sherry.sun@nxp.com/mbox/","series":[{"id":499380,"url":"http://patchwork.ozlabs.org/api/1.2/series/499380/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499380","date":"2026-04-10T02:30:43","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":12,"mbox":"http://patchwork.ozlabs.org/series/499380/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221636/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221636/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V12 09/12] arm64: dts: imx8mp: Add Root Port node and PERST\n property","Date":"Fri, 10 Apr 2026 10:30:52 +0800","Message-Id":"<20260410023055.2439146-10-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260410023055.2439146-1-sherry.sun@nxp.com>","References":"<20260410023055.2439146-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"SI1PR02CA0020.apcprd02.prod.outlook.com\n (2603:1096:4:1f4::9) To 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7r7xvPRdlof1SKjVHK3xKBqzSUC/dYWu0OzsVeAlpRK/JgiDw52dhw8ze5gzQXhW75NgtpyJyPqY8RAnfnelaSNLl/gtV4IQt2hSXkJFKsWES/RGu5kd5YqC+nyb48PtJBlasJmFt26MuozcIjBfmFEy9NBwNpBZ+ccoEL/z1zitHFo4H+OHuBXyU4nhKIOR7bM+q6jfup68WipUBS/Hg+a6f/9Is2x3FgR/cvP3sPzACz3vjGgJfEaJtXHICtT3bpqdFDXiKHZcZYC61gEOj6w5uWSR4iAXzMUl0wl52rmJmiBadSYUWJ8swlD4XHhOJrdMA2ANkfslMbJSXuhOeZvB+Lp43JUsKT/PiKbDe4g4z9c/NY2X82mKolhWnZmBrbYw31IM9KsbMqSoojcY6gmr4XUxD3PkmOU3H3jtcTNUowDHfPyFXRBqMCbRTU4WLtdZkvDX4o8mRv+ycspRTm/zQ64NWWkzWchUo4tQ7COQfLmVuK8Wox/IrrdT1+FiPPE812OFK6EzaFPX47OhNSVL5mIkqYAdpFKLixZeLSv5OoDYCe05sCnVHIc5/xmvj0O8A7Odn+HyVpoUh/0Vv54DUUwSP0NiE2WcmJF3Gzcac+E2dtYhs/7PS72dIj0j0l7oy6Q0Cnvs9UvDIl5rkL6k5gYBonvGzdFMCmUk7Ld0rYsNluF8iq24xJq27KU2AdkPhV4mTy8++xGhlte3J53tAnNLVmQOKFhmI4SQ54+JLYFy44y8uzHf4vZ0CrY6luoYdYvYIJktZYrIHn2QXulGMIosENgWIYYqyzAMTTo7z1SlNb7iMMlArwb4iNXzD2ZAa26lPo5HnA6rroQmujURKmw/oMaMkZHAJ5vdrOB8S4VqljoAUSBoQpGXGcgotfga59/sbsSLCX32rNYfDsQM9h5OIm3dFZR35h/rL0Bg9EdA7WUFcpOj8gsZulX5c61nF9jmWiNRaS/Jn/9OOb48jIM8J1J2BmxJJ6O2ArR9IkzIYeozN1d2BzS6SWwX+BwdDuPNgH0dsINbrU1dbBWQ0vDShoFzICe3Us6xzw15gjhvb/s7z3GUL+F2lIJGVX4cB6Up47T5lrBQyC7HGwSUY7P6d06mfYclWgbm+xwQ5rSGhbupYakUMD4ViaGHNEQSs0LCw7BgPig8LzMTfmFg12EhiK/ZJzFOhsJIrkNJak09w1S/modU6wjAkkb/huBnE4aakGOzJ5kBjxDXt2YC1xqzqmt+lD7YGedgZxEJsDeN1746dyUXAKTbnlgmdqDvE3KnD8NXUY2bEuMuT1OoOVdTnBsE18+290TM1ZW920EfhXGUMyhF+sgXIFMKPx8htXKXSMvHa5iBZvxWn1iAmzxZl7ZsdD8psAlvudjxYFkP/AX0iK93/+pTMzENtL4r7Ass3re2yhCs2cPk16Vxt9xzh0C1Qmtrc+lVKlFa5Xs5Ub61qWzGKI0+EAuqbld/mMGQYdFRjaNlYB89KfuvpoyHh7TBQlyoEHW/znxs2CSYYZZWED4hcsCAoZvB8zlAI7z5EPGhisrPKYs7qrtOeScY9V3IZ77u3zJcJfY/xAV5XYcXTKS2dnd6SxmIs2Tp6CshMurY1hbc6uylUTMuLCKCsUhLipOUKe3M1HKsElT24eW/9YcDQFp0esEAIemrWC0Hy9dwQ1+221BUi/dBWl954VXR10aS/V07cXWjy2x5jfkYBz1j0EH4CFQpjNay6J6mLZ9Kps75O8x2fg==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 797a701f-ea8a-478b-bf28-08de96a921d1","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"10 Apr 2026 02:30:29.6685\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n Fxe7igsOB6Pfux0kLeveo1gNbGwxdtmDpYl0JwliviI5FPfzhQS58cUBx6B4RuJ8DTZyDzSDwrkjWm4sJjABuw==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AS5PR04MB9826"},"content":"Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun \n---\n arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 +++++\n arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +++++++++++\n 2 files changed, 16 insertions(+)","diff":"diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts\nindex 2feb5b18645c..a7f3acdc36d1 100644\n--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts\n@@ -770,6 +770,7 @@ &pcie_phy {\n &pcie0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pcie0>;\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcie0>;\n \tvpcie3v3aux-supply = <®_pcie0>;\n@@ -783,6 +784,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcie0_port0 {\n+\treset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;\n+};\n+\n &pwm1 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pwm1>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi\nindex 90d7bb8f5619..5ce2825182fd 100644\n--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi\n@@ -2265,6 +2265,17 @@ pcie0: pcie: pcie@33800000 {\n \t\t\tphys = <&pcie_phy>;\n \t\t\tphy-names = \"pcie-phy\";\n \t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcie0_port0: pcie@0 {\n+\t\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\t\tdevice_type = \"pci\";\n+\t\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t\t#address-cells = <3>;\n+\t\t\t\t#size-cells = <2>;\n+\t\t\t\tranges;\n+\t\t\t};\n \t\t};\n \n \t\tpcie0_ep: pcie_ep: pcie-ep@33800000 {\n","prefixes":["V12","09/12"]}