{"id":2221632,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221632/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410023055.2439146-2-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410023055.2439146-2-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-10T02:30:44","name":"[V12,01/12] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3251068ee9e53f63b745075ba6ef7f82383237bb","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/1.2/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410023055.2439146-2-sherry.sun@nxp.com/mbox/","series":[{"id":499380,"url":"http://patchwork.ozlabs.org/api/1.2/series/499380/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499380","date":"2026-04-10T02:30:43","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":12,"mbox":"http://patchwork.ozlabs.org/series/499380/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221632/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221632/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V12 01/12] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in\n Root Port node","Date":"Fri, 10 Apr 2026 10:30:44 +0800","Message-Id":"<20260410023055.2439146-2-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260410023055.2439146-1-sherry.sun@nxp.com>","References":"<20260410023055.2439146-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"SI1PR02CA0020.apcprd02.prod.outlook.com\n (2603:1096:4:1f4::9) To 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9b60fd27-47f6-4425-d930-08de96a904f6","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"10 Apr 2026 02:29:41.2575\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n 0GlghRcu5/W+YpX6F00SU7pdovgmzKl9S6D7J8FEgIW84F+fklr7SFFaZ0Xjj2cEo5NmM8IX2Z5zIGRjgTQI3Q==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AS5PR04MB9826"},"content":"Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property\nfor the Root Port node.\n\nThe reset-gpios property is already defined in pci-bus-common.yaml for\nPERST#, so use it instead of the local reset-gpio property. Keep the\nexisting reset-gpio property in the bridge node for backward\ncompatibility, but mark it as deprecated.\n\nSigned-off-by: Sherry Sun \nReviewed-by: Rob Herring (Arm) \n---\n .../bindings/pci/fsl,imx6q-pcie.yaml | 32 +++++++++++++++++++\n 1 file changed, 32 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\nindex 12a01f7a5744..d1a2526f43dc 100644\n--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n@@ -59,16 +59,34 @@ properties:\n - const: dma\n \n reset-gpio:\n+ deprecated: true\n description: Should specify the GPIO for controlling the PCI bus device\n reset signal. It's not polarity aware and defaults to active-low reset\n sequence (L=reset state, H=operation state) (optional required).\n+ This property is deprecated, instead of referencing this property from the\n+ host bridge node, use the reset-gpios property from the root port node.\n \n reset-gpio-active-high:\n+ deprecated: true\n description: If present then the reset sequence using the GPIO\n specified in the \"reset-gpio\" property is reversed (H=reset state,\n L=operation state) (optional required).\n+ This property is deprecated along with the reset-gpio property above, use\n+ the reset-gpios property from the root port node.\n type: boolean\n \n+ pcie@0:\n+ description:\n+ Describe the i.MX6 PCIe Root Port.\n+ type: object\n+ $ref: /schemas/pci/pci-pci-bridge.yaml#\n+\n+ properties:\n+ reg:\n+ maxItems: 1\n+\n+ unevaluatedProperties: false\n+\n required:\n - compatible\n - reg\n@@ -229,6 +247,7 @@ unevaluatedProperties: false\n examples:\n - |\n #include \n+ #include \n #include \n \n pcie: pcie@1ffc000 {\n@@ -255,5 +274,18 @@ examples:\n <&clks IMX6QDL_CLK_LVDS1_GATE>,\n <&clks IMX6QDL_CLK_PCIE_REF_125M>;\n clock-names = \"pcie\", \"pcie_bus\", \"pcie_phy\";\n+\n+ pcie_port0: pcie@0 {\n+ compatible = \"pciclass,0604\";\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;\n+ };\n };\n ...\n","prefixes":["V12","01/12"]}