{"id":2221555,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221555/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260409185254.3869808-2-zhiw@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260409185254.3869808-2-zhiw@nvidia.com>","list_archive_url":null,"date":"2026-04-09T18:52:54","name":"[v3,1/1] rust: pci: add extended capability and SR-IOV support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9b70d0982c1d54f1a0eb2686feab0215ad9fee9a","submitter":{"id":88076,"url":"http://patchwork.ozlabs.org/api/1.2/people/88076/?format=json","name":"Zhi Wang","email":"zhiw@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260409185254.3869808-2-zhiw@nvidia.com/mbox/","series":[{"id":499342,"url":"http://patchwork.ozlabs.org/api/1.2/series/499342/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499342","date":"2026-04-09T18:52:54","name":"Rust PCI capability infrastructure and SR-IOV support","version":3,"mbox":"http://patchwork.ozlabs.org/series/499342/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221555/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221555/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=hpGya+Uw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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It\ndelegates IoCapable to the underlying ConfigSpace, so io_project!/io_read!\n/io_write! work directly on capability register structs.\n\nAlso add a rust helper for the PCI_EXT_CAP_NEXT() macro.\n\nLink: https://lore.kernel.org/rust-for-linux/20260126215957.541180-1-zhiw@nvidia.com/\nCc: Gary Guo \nSigned-off-by: Zhi Wang \n---\n rust/helpers/pci.c | 5 +\n rust/kernel/pci.rs | 7 ++\n rust/kernel/pci/cap.rs | 256 +++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 268 insertions(+)\n create mode 100644 rust/kernel/pci/cap.rs","diff":"diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c\nindex e44905317d75..5043c9909d44 100644\n--- a/rust/helpers/pci.c\n+++ b/rust/helpers/pci.c\n@@ -24,6 +24,11 @@ __rust_helper bool rust_helper_dev_is_pci(const struct device *dev)\n \treturn dev_is_pci(dev);\n }\n \n+__rust_helper u32 rust_helper_pci_ext_cap_next(u32 header)\n+{\n+\treturn PCI_EXT_CAP_NEXT(header);\n+}\n+\n #ifndef CONFIG_PCI_MSI\n __rust_helper int rust_helper_pci_alloc_irq_vectors(struct pci_dev *dev,\n \t\t\t\t\t\t unsigned int min_vecs,\ndiff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs\nindex af74ddff6114..962c6656dc96 100644\n--- a/rust/kernel/pci.rs\n+++ b/rust/kernel/pci.rs\n@@ -31,10 +31,17 @@\n },\n };\n \n+mod cap;\n mod id;\n mod io;\n mod irq;\n \n+pub use self::cap::{\n+ ExtCapId,\n+ ExtCapability,\n+ ExtSriovCapability,\n+ ExtSriovRegs, //\n+};\n pub use self::id::{\n Class,\n ClassMask,\ndiff --git a/rust/kernel/pci/cap.rs b/rust/kernel/pci/cap.rs\nnew file mode 100644\nindex 000000000000..1a25ef4cc633\n--- /dev/null\n+++ b/rust/kernel/pci/cap.rs\n@@ -0,0 +1,256 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+//! PCI extended capability support.\n+\n+use super::{\n+ ConfigSpace,\n+ Extended, //\n+};\n+use crate::{\n+ bindings,\n+ io::{\n+ Io,\n+ IoCapable,\n+ Region, //\n+ },\n+ prelude::*,\n+ ptr::KnownSize, //\n+};\n+\n+/// PCI extended capability IDs.\n+#[repr(u16)]\n+#[derive(Debug, Clone, Copy, PartialEq, Eq)]\n+pub enum ExtCapId {\n+ /// Single Root I/O Virtualization.\n+ // CAST: `PCI_EXT_CAP_ID_SRIOV` is `0x10`, which fits in `u16`.\n+ Sriov = bindings::PCI_EXT_CAP_ID_SRIOV as u16,\n+}\n+\n+impl ExtCapId {\n+ fn as_raw(self) -> u16 {\n+ self as u16\n+ }\n+}\n+\n+/// An extended PCI capability that implements [`Io`].\n+///\n+/// # Examples\n+///\n+/// ```no_run\n+/// use kernel::pci::{\n+/// self,\n+/// ExtSriovCapability, //\n+/// };\n+/// use kernel::io::Io;\n+///\n+/// fn probe_sriov(pdev: &pci::Device) -> Result<(), kernel::error::Error> {\n+/// let config = pdev.config_space_extended()?;\n+/// let sriov = ExtSriovCapability::find(&config)?;\n+///\n+/// let total_vfs = kernel::io_read!(&sriov, .total_vfs);\n+/// let vf_offset = kernel::io_read!(&sriov, .vf_offset);\n+/// let bar0 = kernel::io_read!(&sriov, .vf_bar[0]);\n+/// kernel::io_write!(&sriov, .num_vfs, 4u16);\n+/// let bar0_64 = sriov.read_vf_bar64(0)?;\n+///\n+/// Ok(())\n+/// }\n+/// ```\n+///\n+/// # Invariants\n+///\n+/// `ptr` is within the device's extended configuration space at a valid\n+/// capability. For sized `T`, the region is at least `size_of::()` bytes.\n+pub struct ExtCapability<'a, T: ?Sized + KnownSize = Region<0>> {\n+ config: &'a ConfigSpace<'a, Extended>,\n+ ptr: *mut T,\n+}\n+\n+impl Io for ExtCapability<'_, T> {\n+ type Type = T;\n+\n+ #[inline]\n+ fn as_ptr(&self) -> *mut T {\n+ self.ptr\n+ }\n+}\n+\n+macro_rules! impl_ext_cap_io_capable {\n+ ($ty:ty) => {\n+ impl IoCapable<$ty> for ExtCapability<'_, T> {\n+ #[inline]\n+ unsafe fn io_read(&self, address: *mut $ty) -> $ty {\n+ // SAFETY: The caller guarantees `address` is within bounds of\n+ // this capability, which is within the config space.\n+ unsafe { self.config.io_read(address) }\n+ }\n+\n+ #[inline]\n+ unsafe fn io_write(&self, value: $ty, address: *mut $ty) {\n+ // SAFETY: The caller guarantees `address` is within bounds of\n+ // this capability, which is within the config space.\n+ unsafe { self.config.io_write(value, address) }\n+ }\n+ }\n+ };\n+}\n+\n+impl_ext_cap_io_capable!(u8);\n+impl_ext_cap_io_capable!(u16);\n+impl_ext_cap_io_capable!(u32);\n+\n+impl<'a> ExtCapability<'a> {\n+ /// Base offset of this capability in configuration space.\n+ #[inline]\n+ pub fn offset(&self) -> usize {\n+ self.ptr.addr()\n+ }\n+\n+ /// Size of this capability region in bytes.\n+ #[inline]\n+ pub fn size(&self) -> usize {\n+ KnownSize::size(self.ptr)\n+ }\n+\n+ /// Cast to a typed capability, checking that the region is large enough.\n+ pub fn cast_sized(self) -> Result> {\n+ if self.size() < core::mem::size_of::() {\n+ return Err(EINVAL);\n+ }\n+\n+ // INVARIANT: `self` already satisfies the invariant (ptr is within extended config\n+ // space at a valid capability), and the size check above guarantees the region is at\n+ // least `size_of::()` bytes.\n+ Ok(ExtCapability {\n+ config: self.config,\n+ ptr: core::ptr::without_provenance_mut(self.offset()),\n+ })\n+ }\n+}\n+\n+impl ConfigSpace<'_, Extended> {\n+ /// Finds an extended capability by ID, returning an untyped [`ExtCapability`].\n+ pub fn find_ext_capability(&self, cap: ExtCapId) -> Result> {\n+ let offset = usize::from(\n+ // SAFETY: `self.pdev` is valid by the type invariant of `ConfigSpace`.\n+ unsafe {\n+ bindings::pci_find_ext_capability(self.pdev.as_raw(), i32::from(cap.as_raw()))\n+ },\n+ );\n+\n+ if offset == 0 {\n+ return Err(ENODEV);\n+ }\n+\n+ Ok(self.make_ext_capability(offset))\n+ }\n+\n+ /// Finds the next extended capability with `cap` after `start`.\n+ pub fn find_next_ext_capability(&self, start: u16, cap: ExtCapId) -> Result> {\n+ let offset = usize::from(\n+ // SAFETY: `self.pdev` is valid by the type invariant of `ConfigSpace`.\n+ unsafe {\n+ bindings::pci_find_next_ext_capability(\n+ self.pdev.as_raw(),\n+ start,\n+ i32::from(cap.as_raw()),\n+ )\n+ },\n+ );\n+\n+ if offset == 0 {\n+ return Err(ENODEV);\n+ }\n+\n+ Ok(self.make_ext_capability(offset))\n+ }\n+\n+ fn make_ext_capability(&self, offset: usize) -> ExtCapability<'_> {\n+ let size = self.calculate_ext_cap_size(offset);\n+\n+ let ptr = core::ptr::slice_from_raw_parts_mut::(\n+ core::ptr::without_provenance_mut(offset),\n+ size,\n+ // CAST: `Region<0>` is a DST like `[u8]`, so this pointer cast preserves metadata.\n+ ) as *mut Region<0>;\n+\n+ // INVARIANT: `offset` was returned by `pci_find_ext_capability` /\n+ // `pci_find_next_ext_capability`, which guarantees it points to a valid capability\n+ // within the extended configuration space. `size` is bounded by the next capability\n+ // offset or the end of the configuration space.\n+ ExtCapability { config: self, ptr }\n+ }\n+\n+ fn calculate_ext_cap_size(&self, offset: usize) -> usize {\n+ let header = self.try_read32(offset).unwrap_or(0);\n+ // SAFETY: Pure bit manipulation, no preconditions.\n+ // CAST: The next-cap pointer is a 12-bit field (max 0xFFC), always fits in `usize`.\n+ let next_ptr = unsafe { bindings::pci_ext_cap_next(header) } as usize;\n+\n+ if next_ptr > offset {\n+ next_ptr - offset\n+ } else {\n+ KnownSize::size(self.as_ptr()) - offset\n+ }\n+ }\n+}\n+\n+/// SR-IOV register layout per PCIe spec (64 bytes starting at cap offset).\n+#[repr(C)]\n+pub struct ExtSriovRegs {\n+ /// Extended capability header.\n+ pub header: u32,\n+ /// SR-IOV capabilities.\n+ pub cap: u32,\n+ /// SR-IOV control.\n+ pub ctrl: u16,\n+ /// SR-IOV status.\n+ pub status: u16,\n+ /// Initial VFs.\n+ pub initial_vfs: u16,\n+ /// Total VFs.\n+ pub total_vfs: u16,\n+ /// Number of VFs.\n+ pub num_vfs: u16,\n+ /// Function dependency link.\n+ pub func_dep_link: u16,\n+ /// First VF offset.\n+ pub vf_offset: u16,\n+ /// VF stride.\n+ pub vf_stride: u16,\n+ _reserved: u16,\n+ /// VF device ID.\n+ pub vf_device_id: u16,\n+ /// Supported page sizes.\n+ pub supported_page_sizes: u32,\n+ /// System page size.\n+ pub system_page_size: u32,\n+ /// VF BARs (BAR0–BAR5).\n+ pub vf_bar: [u32; 6],\n+ /// VF migration state array offset.\n+ pub migration_state: u32,\n+}\n+\n+/// SR-IOV capability. See [`ExtCapability`] for usage.\n+pub type ExtSriovCapability<'a> = ExtCapability<'a, ExtSriovRegs>;\n+\n+impl ExtCapability<'_, ExtSriovRegs> {\n+ /// Find the SR-IOV capability, or `ENODEV` if not present.\n+ #[inline]\n+ pub fn find<'a>(\n+ config: &'a ConfigSpace<'_, Extended>,\n+ ) -> Result> {\n+ config.find_ext_capability(ExtCapId::Sriov)?.cast_sized()\n+ }\n+\n+ /// Reads a 64-bit VF BAR from two consecutive 32-bit slots.\n+ #[inline]\n+ pub fn read_vf_bar64(&self, bar_index: usize) -> Result {\n+ if bar_index >= 5 {\n+ return Err(EINVAL);\n+ }\n+ let low = crate::io_read!(self, .vf_bar[bar_index]?);\n+ let high = crate::io_read!(self, .vf_bar[bar_index + 1]?);\n+ Ok((u64::from(high) << 32) | u64::from(low))\n+ }\n+}\n","prefixes":["v3","1/1"]}