{"id":2221491,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221491/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409142137.58349-2-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260409142137.58349-2-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-09T14:21:33","name":"[PULL,1/4] ati-vga: Fix pitch and offset registers mask","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"903327ab402135b510091ea29a92c9a7a92d4e2b","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.2/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409142137.58349-2-philmd@linaro.org/mbox/","series":[{"id":499309,"url":"http://patchwork.ozlabs.org/api/1.2/series/499309/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499309","date":"2026-04-09T14:21:32","name":"[PULL,1/4] ati-vga: Fix pitch and offset registers mask","version":1,"mbox":"http://patchwork.ozlabs.org/series/499309/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221491/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221491/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Vi26j2sg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: BALATON Zoltan \n\nRemove the Radeon specific masks for offset and pitch registers. While\nthe documentation is not clear about it I believe it is a copy&paste\nerror from the combined DST_PITCH_OFFSET register that has less bits\nso more constrained than the individual registers which should not\nhave this mask.\n\nSigned-off-by: BALATON Zoltan \nMessage-ID: <20260404111318.8334E596A22@zero.eik.bme.hu>\nSigned-off-by: Philippe Mathieu-Daudé \n---\n hw/display/ati.c | 16 ++--------------\n 1 file changed, 2 insertions(+), 14 deletions(-)","diff":"diff --git a/hw/display/ati.c b/hw/display/ati.c\nindex 7bb57c44d95..88a5bbbf07a 100644\n--- a/hw/display/ati.c\n+++ b/hw/display/ati.c\n@@ -820,18 +820,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,\n ati_cursor_define(s);\n break;\n case DST_OFFSET:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.dst_offset = data & 0xfffffff0;\n- } else {\n- s->regs.dst_offset = data & 0xfffffc00;\n- }\n break;\n case DST_PITCH:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.dst_pitch = data & 0x3fff;\n+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.dst_tile = (data >> 16) & 1;\n- } else {\n- s->regs.dst_pitch = data & 0x3ff0;\n }\n break;\n case DST_TILE:\n@@ -941,18 +935,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,\n s->regs.dst_height = (data >> 16) & 0x3fff;\n break;\n case SRC_OFFSET:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.src_offset = data & 0xfffffff0;\n- } else {\n- s->regs.src_offset = data & 0xfffffc00;\n- }\n break;\n case SRC_PITCH:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.src_pitch = data & 0x3fff;\n+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.src_tile = (data >> 16) & 1;\n- } else {\n- s->regs.src_pitch = data & 0x3ff0;\n }\n break;\n case DP_BRUSH_BKGD_CLR:\n","prefixes":["PULL","1/4"]}