{"id":2221434,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221434/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260409131340.168556-6-pshete@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260409131340.168556-6-pshete@nvidia.com>","list_archive_url":null,"date":"2026-04-09T13:13:39","name":"[5/6] pinctrl: tegra: Add Tegra264 pinmux driver","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2501869ea59cb47626b834518892a050f301bbf9","submitter":{"id":82424,"url":"http://patchwork.ozlabs.org/api/1.2/people/82424/?format=json","name":"Prathamesh Shete","email":"pshete@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260409131340.168556-6-pshete@nvidia.com/mbox/","series":[{"id":499291,"url":"http://patchwork.ozlabs.org/api/1.2/series/499291/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=499291","date":"2026-04-09T13:13:34","name":"Add Tegra238 and Tegra264 pinctrl support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499291/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221434/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221434/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=MVCoturD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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This driver controls the pin multiplexing\n+\t and configuration for the MAIN, AON and UPHY pin controllers found\n+\t on Tegra264.\n+\n config PINCTRL_TEGRA_XUSB\n \tdef_bool y if ARCH_TEGRA\n \tselect GENERIC_PHY\ndiff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile\nindex ce700bbcbf6e..71ade768bf9c 100644\n--- a/drivers/pinctrl/tegra/Makefile\n+++ b/drivers/pinctrl/tegra/Makefile\n@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_TEGRA186)\t\t+= pinctrl-tegra186.o\n obj-$(CONFIG_PINCTRL_TEGRA194)\t\t+= pinctrl-tegra194.o\n obj-$(CONFIG_PINCTRL_TEGRA234)\t\t+= pinctrl-tegra234.o\n obj-$(CONFIG_PINCTRL_TEGRA238)\t\t+= pinctrl-tegra238.o\n+obj-$(CONFIG_PINCTRL_TEGRA264)\t\t+= pinctrl-tegra264.o\n obj-$(CONFIG_PINCTRL_TEGRA_XUSB)\t+= pinctrl-tegra-xusb.o\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra264.c b/drivers/pinctrl/tegra/pinctrl-tegra264.c\nnew file mode 100644\nindex 000000000000..5a0c91aaba3a\n--- /dev/null\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra264.c\n@@ -0,0 +1,2216 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Pinctrl data for the NVIDIA Tegra264 pinmux\n+ *\n+ * Copyright (c) 2024-2026, NVIDIA CORPORATION. All rights reserved.\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#include \"pinctrl-tegra.h\"\n+\n+/* Define unique ID for each pins */\n+enum {\n+\tTEGRA_PIN_PEX_L4_CLKREQ_N_PD0,\n+\tTEGRA_PIN_PEX_L4_RST_N_PD1,\n+\tTEGRA_PIN_PEX_L5_CLKREQ_N_PD2,\n+\tTEGRA_PIN_PEX_L5_RST_N_PD3,\n+\tTEGRA_PIN_ETH0_MDIO_PD4,\n+\tTEGRA_PIN_ETH0_MDC_PD5,\n+\tTEGRA_PIN_ETH3_MDIO_PD6,\n+\tTEGRA_PIN_ETH3_MDC_PD7,\n+\tTEGRA_PIN_ETH1_MDIO_PE0,\n+\tTEGRA_PIN_ETH1_MDC_PE1,\n+\tTEGRA_PIN_ETH2_MDIO_PE2,\n+\tTEGRA_PIN_ETH2_MDC_PE3,\n+\tTEGRA_PIN_PEX_L1_CLKREQ_N_PB0,\n+\tTEGRA_PIN_PEX_L1_RST_N_PB1,\n+\tTEGRA_PIN_PEX_L2_CLKREQ_N_PB2,\n+\tTEGRA_PIN_PEX_L2_RST_N_PB3,\n+\tTEGRA_PIN_PEX_L3_CLKREQ_N_PB4,\n+\tTEGRA_PIN_PEX_L3_RST_N_PB5,\n+\tTEGRA_PIN_SOC_GPIO113_PB6,\n+\tTEGRA_PIN_SOC_GPIO114_PB7,\n+\tTEGRA_PIN_SGMII0_SMA_MDIO_PC0,\n+\tTEGRA_PIN_SGMII0_SMA_MDC_PC1,\n+\tTEGRA_PIN_PEX_WAKE_N_PC2,\n+\tTEGRA_PIN_PWM1_PA0,\n+\tTEGRA_PIN_PWM6_PA1,\n+\tTEGRA_PIN_PWM7_PA2,\n+\tTEGRA_PIN_PWM8_PA3,\n+\tTEGRA_PIN_UFS0_REF_CLK_PA4,\n+\tTEGRA_PIN_UFS0_RST_N_PA5,\n+};\n+\n+enum {\n+\tTEGRA_PIN_SOC_GPIO250_PF0,\n+\tTEGRA_PIN_SOC_GPIO251_PF1,\n+\tTEGRA_PIN_SOC_GPIO252_PF2,\n+\tTEGRA_PIN_DP_AUX_CH0_HPD_PF3,\n+\tTEGRA_PIN_DP_AUX_CH1_HPD_PF4,\n+\tTEGRA_PIN_DP_AUX_CH2_HPD_PF5,\n+\tTEGRA_PIN_DP_AUX_CH3_HPD_PF6,\n+\tTEGRA_PIN_PWM2_PF7,\n+\tTEGRA_PIN_PWM3_PG0,\n+\tTEGRA_PIN_GEN7_I2C_SCL_PG1,\n+\tTEGRA_PIN_GEN7_I2C_SDA_PG2,\n+\tTEGRA_PIN_GEN9_I2C_SCL_PG3,\n+\tTEGRA_PIN_GEN9_I2C_SDA_PG4,\n+\tTEGRA_PIN_SDMMC1_CLK_PX0,\n+\tTEGRA_PIN_SDMMC1_CMD_PX1,\n+\tTEGRA_PIN_SDMMC1_DAT0_PX2,\n+\tTEGRA_PIN_SDMMC1_DAT1_PX3,\n+\tTEGRA_PIN_SDMMC1_DAT2_PX4,\n+\tTEGRA_PIN_SDMMC1_DAT3_PX5,\n+\tTEGRA_PIN_SDMMC1_COMP,\n+\tTEGRA_PIN_SOC_GPIO124_PL0,\n+\tTEGRA_PIN_SOC_GPIO125_PL1,\n+\tTEGRA_PIN_FAN_TACH0_PL2,\n+\tTEGRA_PIN_SOC_GPIO127_PL3,\n+\tTEGRA_PIN_SOC_GPIO128_PL4,\n+\tTEGRA_PIN_SOC_GPIO129_PL5,\n+\tTEGRA_PIN_SOC_GPIO130_PL6,\n+\tTEGRA_PIN_SOC_GPIO131_PL7,\n+\tTEGRA_PIN_GP_PWM9_PM0,\n+\tTEGRA_PIN_SOC_GPIO133_PM1,\n+\tTEGRA_PIN_UART9_TX_PM2,\n+\tTEGRA_PIN_UART9_RX_PM3,\n+\tTEGRA_PIN_UART9_RTS_N_PM4,\n+\tTEGRA_PIN_UART9_CTS_N_PM5,\n+\tTEGRA_PIN_SOC_GPIO170_PU0,\n+\tTEGRA_PIN_SOC_GPIO171_PU1,\n+\tTEGRA_PIN_SOC_GPIO172_PU2,\n+\tTEGRA_PIN_SOC_GPIO173_PU3,\n+\tTEGRA_PIN_SOC_GPIO174_PU4,\n+\tTEGRA_PIN_SOC_GPIO175_PU5,\n+\tTEGRA_PIN_SOC_GPIO176_PU6,\n+\tTEGRA_PIN_SOC_GPIO177_PU7,\n+\tTEGRA_PIN_SOC_GPIO178_PV0,\n+\tTEGRA_PIN_PWM10_PV1,\n+\tTEGRA_PIN_UART4_TX_PV2,\n+\tTEGRA_PIN_UART4_RX_PV3,\n+\tTEGRA_PIN_UART4_RTS_N_PV4,\n+\tTEGRA_PIN_UART4_CTS_N_PV5,\n+\tTEGRA_PIN_DAP2_CLK_PV6,\n+\tTEGRA_PIN_DAP2_DIN_PV7,\n+\tTEGRA_PIN_DAP2_DOUT_PW0,\n+\tTEGRA_PIN_DAP2_FS_PW1,\n+\tTEGRA_PIN_GEN1_I2C_SCL_PW2,\n+\tTEGRA_PIN_GEN1_I2C_SDA_PW3,\n+\tTEGRA_PIN_GEN0_I2C_SCL_PW4,\n+\tTEGRA_PIN_GEN0_I2C_SDA_PW5,\n+\tTEGRA_PIN_PWR_I2C_SCL_PW6,\n+\tTEGRA_PIN_PWR_I2C_SDA_PW7,\n+\tTEGRA_PIN_SOC_GPIO138_PP0,\n+\tTEGRA_PIN_SOC_GPIO139_PP1,\n+\tTEGRA_PIN_DAP6_SCLK_PP2,\n+\tTEGRA_PIN_DAP6_DOUT_PP3,\n+\tTEGRA_PIN_DAP6_DIN_PP4,\n+\tTEGRA_PIN_DAP6_FS_PP5,\n+\tTEGRA_PIN_DAP4_SCLK_PP6,\n+\tTEGRA_PIN_DAP4_DOUT_PP7,\n+\tTEGRA_PIN_DAP4_DIN_PQ0,\n+\tTEGRA_PIN_DAP4_FS_PQ1,\n+\tTEGRA_PIN_SPI5_SCK_PQ2,\n+\tTEGRA_PIN_SPI5_MISO_PQ3,\n+\tTEGRA_PIN_SPI5_MOSI_PQ4,\n+\tTEGRA_PIN_SPI5_CS0_PQ5,\n+\tTEGRA_PIN_SOC_GPIO152_PQ6,\n+\tTEGRA_PIN_SOC_GPIO153_PQ7,\n+\tTEGRA_PIN_AUD_MCLK_PR0,\n+\tTEGRA_PIN_SOC_GPIO155_PR1,\n+\tTEGRA_PIN_DAP1_SCLK_PR2,\n+\tTEGRA_PIN_DAP1_OUT_PR3,\n+\tTEGRA_PIN_DAP1_IN_PR4,\n+\tTEGRA_PIN_DAP1_FS_PR5,\n+\tTEGRA_PIN_GEN11_I2C_SCL_PR6,\n+\tTEGRA_PIN_GEN11_I2C_SDA_PR7,\n+\tTEGRA_PIN_SOC_GPIO350_PS0,\n+\tTEGRA_PIN_SOC_GPIO351_PS1,\n+\tTEGRA_PIN_QSPI0_SCK_PT0,\n+\tTEGRA_PIN_QSPI0_CS_N_PT1,\n+\tTEGRA_PIN_QSPI0_IO0_PT2,\n+\tTEGRA_PIN_QSPI0_IO1_PT3,\n+\tTEGRA_PIN_QSPI0_IO2_PT4,\n+\tTEGRA_PIN_QSPI0_IO3_PT5,\n+\tTEGRA_PIN_SOC_GPIO192_PT6,\n+\tTEGRA_PIN_SOC_GPIO270_PY0,\n+\tTEGRA_PIN_SOC_GPIO271_PY1,\n+\tTEGRA_PIN_SOC_GPIO272_PY2,\n+\tTEGRA_PIN_SOC_GPIO273_PY3,\n+\tTEGRA_PIN_SOC_GPIO274_PY4,\n+\tTEGRA_PIN_SOC_GPIO275_PY5,\n+\tTEGRA_PIN_SOC_GPIO276_PY6,\n+\tTEGRA_PIN_SOC_GPIO277_PY7,\n+\tTEGRA_PIN_SOC_GPIO278_PZ0,\n+\tTEGRA_PIN_SOC_GPIO279_PZ1,\n+\tTEGRA_PIN_XHALT_TRIG_PZ2,\n+\tTEGRA_PIN_SOC_GPIO281_PZ3,\n+\tTEGRA_PIN_SOC_GPIO282_PZ4,\n+\tTEGRA_PIN_SOC_GPIO283_PZ5,\n+\tTEGRA_PIN_SOC_GPIO284_PZ6,\n+\tTEGRA_PIN_SOC_GPIO285_PZ7,\n+\tTEGRA_PIN_SOC_GPIO286_PAL0,\n+\tTEGRA_PIN_SOC_GPIO287_PAL1,\n+\tTEGRA_PIN_SOC_GPIO288_PAL2,\n+\tTEGRA_PIN_CPU_PWR_REQ_PH0,\n+\tTEGRA_PIN_GPU_PWR_REQ_PH1,\n+\tTEGRA_PIN_UART10_TX_PH2,\n+\tTEGRA_PIN_UART10_RX_PH3,\n+\tTEGRA_PIN_UART10_RTS_N_PH4,\n+\tTEGRA_PIN_UART10_CTS_N_PH5,\n+\tTEGRA_PIN_SPI3_SCK_PH6,\n+\tTEGRA_PIN_SPI3_MISO_PH7,\n+\tTEGRA_PIN_SPI3_MOSI_PJ0,\n+\tTEGRA_PIN_SPI3_CS0_PJ1,\n+\tTEGRA_PIN_SPI3_CS3_PJ2,\n+\tTEGRA_PIN_UART5_TX_PJ3,\n+\tTEGRA_PIN_UART5_RX_PJ4,\n+\tTEGRA_PIN_UART5_RTS_N_PJ5,\n+\tTEGRA_PIN_UART5_CTS_N_PJ6,\n+\tTEGRA_PIN_SPI1_SCK_PJ7,\n+\tTEGRA_PIN_SPI1_MISO_PK0,\n+\tTEGRA_PIN_SPI1_MOSI_PK1,\n+\tTEGRA_PIN_SPI1_CS0_PK2,\n+\tTEGRA_PIN_SPI1_CS1_PK3,\n+\tTEGRA_PIN_EXTPERIPH1_CLK_PK4,\n+\tTEGRA_PIN_EXTPERIPH2_CLK_PK5,\n+\tTEGRA_PIN_GEN12_I2C_SCL_PK6,\n+\tTEGRA_PIN_GEN12_I2C_SDA_PK7,\n+};\n+\n+enum {\n+\tTEGRA_PIN_SOC_GPIO00_PAA0,\n+\tTEGRA_PIN_VCOMP_ALERT_PAA1,\n+\tTEGRA_PIN_AO_RETENTION_N_PAA2,\n+\tTEGRA_PIN_BATT_OC_PAA3,\n+\tTEGRA_PIN_BOOTV_CTL_N_PAA4,\n+\tTEGRA_PIN_POWER_ON_PAA5,\n+\tTEGRA_PIN_HDMI_CEC_PAA6,\n+\tTEGRA_PIN_SOC_GPIO07_PAA7,\n+\tTEGRA_PIN_SOC_GPIO08_PBB0,\n+\tTEGRA_PIN_SOC_GPIO09_PBB1,\n+\tTEGRA_PIN_GEN2_I2C_SCL_PCC0,\n+\tTEGRA_PIN_GEN2_I2C_SDA_PCC1,\n+\tTEGRA_PIN_GEN3_I2C_SCL_PCC2,\n+\tTEGRA_PIN_GEN3_I2C_SDA_PCC3,\n+\tTEGRA_PIN_GP_PWM4_PCC4,\n+\tTEGRA_PIN_UART0_TX_PCC5,\n+\tTEGRA_PIN_UART0_RX_PCC6,\n+\tTEGRA_PIN_SPI2_SCK_PCC7,\n+\tTEGRA_PIN_SPI2_MISO_PDD0,\n+\tTEGRA_PIN_SPI2_MOSI_PDD1,\n+\tTEGRA_PIN_SPI2_CS0_N_PDD2,\n+\tTEGRA_PIN_SOC_GPIO21_PDD3,\n+\tTEGRA_PIN_SOC_GPIO22_PDD4,\n+\tTEGRA_PIN_SOC_GPIO23_PDD5,\n+\tTEGRA_PIN_SOC_GPIO24_PDD6,\n+\tTEGRA_PIN_SOC_GPIO25_PDD7,\n+\tTEGRA_PIN_SOC_GPIO26_PEE0,\n+\tTEGRA_PIN_SOC_GPIO27_PEE1,\n+\tTEGRA_PIN_SOC_GPIO28_PEE2,\n+\tTEGRA_PIN_SOC_GPIO29_PEE3,\n+};\n+\n+static const struct pinctrl_pin_desc tegra264_uphy_pins[] = {\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, \"PEX_L4_CLKREQ_N_PD0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PD1, \"PEX_L4_RST_N_PD1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, \"PEX_L5_CLKREQ_N_PD2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PD3, \"PEX_L5_RST_N_PD3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH0_MDIO_PD4, \"ETH0_MDIO_PD4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH0_MDC_PD5, \"ETH0_MDC_PD5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH3_MDIO_PD6, \"ETH3_MDIO_PD6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH3_MDC_PD7, \"ETH3_MDC_PD7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH1_MDIO_PE0, \"ETH1_MDIO_PE0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH1_MDC_PE1, \"ETH1_MDC_PE1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH2_MDIO_PE2, \"ETH2_MDIO_PE2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_ETH2_MDC_PE3, \"ETH2_MDC_PE3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, \"PEX_L1_CLKREQ_N_PB0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PB1, \"PEX_L1_RST_N_PB1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, \"PEX_L2_CLKREQ_N_PB2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PB3, \"PEX_L2_RST_N_PB3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, \"PEX_L3_CLKREQ_N_PB4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PB5, \"PEX_L3_RST_N_PB5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO113_PB6, \"SOC_GPIO113_PB6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO114_PB7, \"SOC_GPIO114_PB7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDIO_PC0, \"SGMII0_SMA_MDIO_PC0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDC_PC1, \"SGMII0_SMA_MDC_PC1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PC2, \"PEX_WAKE_N_PC2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM1_PA0, \"PWM1_PA0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM6_PA1, \"PWM6_PA1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM7_PA2, \"PWM7_PA2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM8_PA3, \"PWM8_PA3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PA4, \"UFS0_REF_CLK_PA4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PA5, \"UFS0_RST_N_PA5\"),\n+};\n+\n+static const struct pinctrl_pin_desc tegra264_main_pins[] = {\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO250_PF0, \"SOC_GPIO250_PF0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO251_PF1, \"SOC_GPIO251_PF1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO252_PF2, \"SOC_GPIO252_PF2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PF3, \"DP_AUX_CH0_HPD_PF3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PF4, \"DP_AUX_CH1_HPD_PF4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PF5, \"DP_AUX_CH2_HPD_PF5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PF6, \"DP_AUX_CH3_HPD_PF6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM2_PF7, \"PWM2_PF7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM3_PG0, \"PWM3_PG0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PG1, \"GEN7_I2C_SCL_PG1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PG2, \"GEN7_I2C_SDA_PG2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PG3, \"GEN9_I2C_SCL_PG3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PG4, \"GEN9_I2C_SDA_PG4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PX0, \"SDMMC1_CLK_PX0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PX1, \"SDMMC1_CMD_PX1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PX2, \"SDMMC1_DAT0_PX2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PX3, \"SDMMC1_DAT1_PX3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PX4, \"SDMMC1_DAT2_PX4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PX5, \"SDMMC1_DAT3_PX5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, \"SDMMC1_COMP\"),\n+\tPINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH0, \"CPU_PWR_REQ_PH0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH1, \"GPU_PWR_REQ_PH1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART10_TX_PH2, \"UART10_TX_PH2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART10_RX_PH3, \"UART10_RX_PH3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART10_RTS_N_PH4, \"UART10_RTS_N_PH4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART10_CTS_N_PH5, \"UART10_CTS_N_PH5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PH6, \"SPI3_SCK_PH6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PH7, \"SPI3_MISO_PH7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PJ0, \"SPI3_MOSI_PJ0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PJ1, \"SPI3_CS0_PJ1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_CS3_PJ2, \"SPI3_CS3_PJ2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_TX_PJ3, \"UART5_TX_PJ3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_RX_PJ4, \"UART5_RX_PJ4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_RTS_N_PJ5, \"UART5_RTS_N_PJ5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_CTS_N_PJ6, \"UART5_CTS_N_PJ6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PJ7, \"SPI1_SCK_PJ7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PK0, \"SPI1_MISO_PK0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PK1, \"SPI1_MOSI_PK1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PK2, \"SPI1_CS0_PK2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PK3, \"SPI1_CS1_PK3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PK4, \"EXTPERIPH1_CLK_PK4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PK5, \"EXTPERIPH2_CLK_PK5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SCL_PK6, \"GEN12_I2C_SCL_PK6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SDA_PK7, \"GEN12_I2C_SDA_PK7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO124_PL0, \"SOC_GPIO124_PL0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO125_PL1, \"SOC_GPIO125_PL1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_FAN_TACH0_PL2, \"FAN_TACH0_PL2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO127_PL3, \"SOC_GPIO127_PL3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO128_PL4, \"SOC_GPIO128_PL4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO129_PL5, \"SOC_GPIO129_PL5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO130_PL6, \"SOC_GPIO130_PL6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO131_PL7, \"SOC_GPIO131_PL7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GP_PWM9_PM0, \"GP_PWM9_PM0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO133_PM1, \"SOC_GPIO133_PM1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART9_TX_PM2, \"UART9_TX_PM2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART9_RX_PM3, \"UART9_RX_PM3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART9_RTS_N_PM4, \"UART9_RTS_N_PM4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART9_CTS_N_PM5, \"UART9_CTS_N_PM5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PT0, \"QSPI0_SCK_PT0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PT1, \"QSPI0_CS_N_PT1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PT2, \"QSPI0_IO0_PT2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PT3, \"QSPI0_IO1_PT3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PT4, \"QSPI0_IO2_PT4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PT5, \"QSPI0_IO3_PT5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO192_PT6, \"SOC_GPIO192_PT6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PU0, \"SOC_GPIO170_PU0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PU1, \"SOC_GPIO171_PU1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PU2, \"SOC_GPIO172_PU2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PU3, \"SOC_GPIO173_PU3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO174_PU4, \"SOC_GPIO174_PU4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO175_PU5, \"SOC_GPIO175_PU5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO176_PU6, \"SOC_GPIO176_PU6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO177_PU7, \"SOC_GPIO177_PU7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO178_PV0, \"SOC_GPIO178_PV0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM10_PV1, \"PWM10_PV1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_TX_PV2, \"UART4_TX_PV2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_RX_PV3, \"UART4_RX_PV3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, \"UART4_RTS_N_PV4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, \"UART4_CTS_N_PV5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, \"DAP2_CLK_PV6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, \"DAP2_DIN_PV7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, \"DAP2_DOUT_PW0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, \"DAP2_FS_PW1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, \"GEN1_I2C_SCL_PW2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, \"GEN1_I2C_SDA_PW3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SCL_PW4, \"GEN0_I2C_SCL_PW4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SDA_PW5, \"GEN0_I2C_SDA_PW5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PW6, \"PWR_I2C_SCL_PW6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PW7, \"PWR_I2C_SDA_PW7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO270_PY0, \"SOC_GPIO270_PY0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO271_PY1, \"SOC_GPIO271_PY1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO272_PY2, \"SOC_GPIO272_PY2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO273_PY3, \"SOC_GPIO273_PY3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO274_PY4, \"SOC_GPIO274_PY4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO275_PY5, \"SOC_GPIO275_PY5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO276_PY6, \"SOC_GPIO276_PY6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO277_PY7, \"SOC_GPIO277_PY7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO278_PZ0, \"SOC_GPIO278_PZ0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO279_PZ1, \"SOC_GPIO279_PZ1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_XHALT_TRIG_PZ2, \"XHALT_TRIG_PZ2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO281_PZ3, \"SOC_GPIO281_PZ3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO282_PZ4, \"SOC_GPIO282_PZ4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO283_PZ5, \"SOC_GPIO283_PZ5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO284_PZ6, \"SOC_GPIO284_PZ6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO285_PZ7, \"SOC_GPIO285_PZ7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO286_PAL0, \"SOC_GPIO286_PAL0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO287_PAL1, \"SOC_GPIO287_PAL1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO288_PAL2, \"SOC_GPIO288_PAL2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO138_PP0, \"SOC_GPIO138_PP0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO139_PP1, \"SOC_GPIO139_PP1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PP2, \"DAP6_SCLK_PP2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PP3, \"DAP6_DOUT_PP3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PP4, \"DAP6_DIN_PP4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP6_FS_PP5, \"DAP6_FS_PP5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP6, \"DAP4_SCLK_PP6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP7, \"DAP4_DOUT_PP7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PQ0, \"DAP4_DIN_PQ0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_FS_PQ1, \"DAP4_FS_PQ1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PQ2, \"SPI5_SCK_PQ2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PQ3, \"SPI5_MISO_PQ3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PQ4, \"SPI5_MOSI_PQ4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PQ5, \"SPI5_CS0_PQ5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PQ6, \"SOC_GPIO152_PQ6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PQ7, \"SOC_GPIO153_PQ7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PR0, \"AUD_MCLK_PR0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PR1, \"SOC_GPIO155_PR1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PR2, \"DAP1_SCLK_PR2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP1_OUT_PR3, \"DAP1_OUT_PR3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP1_IN_PR4, \"DAP1_IN_PR4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP1_FS_PR5, \"DAP1_FS_PR5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SCL_PR6, \"GEN11_I2C_SCL_PR6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SDA_PR7, \"GEN11_I2C_SDA_PR7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO350_PS0, \"SOC_GPIO350_PS0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO351_PS1, \"SOC_GPIO351_PS1\"),\n+\n+};\n+\n+static const struct pinctrl_pin_desc tegra264_aon_pins[] = {\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA0, \"SOC_GPIO00_PAA0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA1, \"VCOMP_ALERT_PAA1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PAA2, \"AO_RETENTION_N_PAA2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA3, \"BATT_OC_PAA3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA4, \"BOOTV_CTL_N_PAA4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_POWER_ON_PAA5, \"POWER_ON_PAA5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PAA6, \"HDMI_CEC_PAA6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PAA7, \"SOC_GPIO07_PAA7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PBB0, \"SOC_GPIO08_PBB0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PBB1, \"SOC_GPIO09_PBB1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC0, \"GEN2_I2C_SCL_PCC0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PCC1, \"GEN2_I2C_SDA_PCC1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PCC2, \"GEN3_I2C_SCL_PCC2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PCC3, \"GEN3_I2C_SDA_PCC3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GP_PWM4_PCC4, \"GP_PWM4_PCC4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART0_TX_PCC5, \"UART0_TX_PCC5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART0_RX_PCC6, \"UART0_RX_PCC6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC7, \"SPI2_SCK_PCC7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PDD0, \"SPI2_MISO_PDD0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PDD1, \"SPI2_MOSI_PDD1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PDD2, \"SPI2_CS0_N_PDD2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PDD3, \"SOC_GPIO21_PDD3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PDD4, \"SOC_GPIO22_PDD4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PDD5, \"SOC_GPIO23_PDD5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PDD6, \"SOC_GPIO24_PDD6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PDD7, \"SOC_GPIO25_PDD7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE0, \"SOC_GPIO26_PEE0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE1, \"SOC_GPIO27_PEE1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PEE2, \"SOC_GPIO28_PEE2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PEE3, \"SOC_GPIO29_PEE3\"),\n+};\n+\n+static const unsigned int soc_gpio250_pf0_pins[] = {\n+\t\tTEGRA_PIN_SOC_GPIO250_PF0,\n+};\n+\n+static const unsigned int soc_gpio251_pf1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO251_PF1,\n+};\n+\n+static const unsigned int soc_gpio252_pf2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO252_PF2,\n+};\n+\n+static const unsigned int dp_aux_ch0_hpd_pf3_pins[] = {\n+\tTEGRA_PIN_DP_AUX_CH0_HPD_PF3,\n+};\n+\n+static const unsigned int dp_aux_ch1_hpd_pf4_pins[] = {\n+\tTEGRA_PIN_DP_AUX_CH1_HPD_PF4,\n+};\n+\n+static const unsigned int dp_aux_ch2_hpd_pf5_pins[] = {\n+\tTEGRA_PIN_DP_AUX_CH2_HPD_PF5,\n+};\n+\n+static const unsigned int dp_aux_ch3_hpd_pf6_pins[] = {\n+\tTEGRA_PIN_DP_AUX_CH3_HPD_PF6,\n+};\n+\n+static const unsigned int pwm2_pf7_pins[] = {\n+\tTEGRA_PIN_PWM2_PF7,\n+};\n+\n+static const unsigned int pwm3_pg0_pins[] = {\n+\tTEGRA_PIN_PWM3_PG0,\n+};\n+\n+static const unsigned int gen7_i2c_scl_pg1_pins[] = {\n+\tTEGRA_PIN_GEN7_I2C_SCL_PG1,\n+};\n+\n+static const unsigned int gen7_i2c_sda_pg2_pins[] = {\n+\tTEGRA_PIN_GEN7_I2C_SDA_PG2,\n+};\n+\n+static const unsigned int gen9_i2c_scl_pg3_pins[] = {\n+\tTEGRA_PIN_GEN9_I2C_SCL_PG3,\n+};\n+\n+static const unsigned int gen9_i2c_sda_pg4_pins[] = {\n+\tTEGRA_PIN_GEN9_I2C_SDA_PG4,\n+};\n+\n+static const unsigned int pwm1_pa0_pins[] = {\n+\tTEGRA_PIN_PWM1_PA0,\n+};\n+\n+static const unsigned int pwm6_pa1_pins[] = {\n+\tTEGRA_PIN_PWM6_PA1,\n+};\n+\n+static const unsigned int pwm7_pa2_pins[] = {\n+\tTEGRA_PIN_PWM7_PA2,\n+};\n+\n+static const unsigned int pwm8_pa3_pins[] = {\n+\tTEGRA_PIN_PWM8_PA3,\n+};\n+\n+static const unsigned int ufs0_ref_clk_pa4_pins[] = {\n+\tTEGRA_PIN_UFS0_REF_CLK_PA4,\n+};\n+\n+static const unsigned int ufs0_rst_n_pa5_pins[] = {\n+\tTEGRA_PIN_UFS0_RST_N_PA5,\n+};\n+\n+static const unsigned int pex_l1_clkreq_n_pb0_pins[] = {\n+\tTEGRA_PIN_PEX_L1_CLKREQ_N_PB0,\n+};\n+\n+static const unsigned int pex_l1_rst_n_pb1_pins[] = {\n+\tTEGRA_PIN_PEX_L1_RST_N_PB1,\n+};\n+\n+static const unsigned int pex_l2_clkreq_n_pb2_pins[] = {\n+\tTEGRA_PIN_PEX_L2_CLKREQ_N_PB2,\n+};\n+\n+static const unsigned int pex_l2_rst_n_pb3_pins[] = {\n+\tTEGRA_PIN_PEX_L2_RST_N_PB3,\n+};\n+\n+static const unsigned int pex_l3_clkreq_n_pb4_pins[] = {\n+\tTEGRA_PIN_PEX_L3_CLKREQ_N_PB4,\n+};\n+\n+static const unsigned int pex_l3_rst_n_pb5_pins[] = {\n+\tTEGRA_PIN_PEX_L3_RST_N_PB5,\n+};\n+\n+static const unsigned int soc_gpio113_pb6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO113_PB6,\n+};\n+\n+static const unsigned int soc_gpio114_pb7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO114_PB7,\n+};\n+\n+static const unsigned int sgmii0_sma_mdio_pc0_pins[] = {\n+\tTEGRA_PIN_SGMII0_SMA_MDIO_PC0,\n+};\n+\n+static const unsigned int sgmii0_sma_mdc_pc1_pins[] = {\n+\tTEGRA_PIN_SGMII0_SMA_MDC_PC1,\n+};\n+\n+static const unsigned int pex_wake_n_pc2_pins[] = {\n+\tTEGRA_PIN_PEX_WAKE_N_PC2,\n+};\n+\n+static const unsigned int pex_l4_clkreq_n_pd0_pins[] = {\n+\tTEGRA_PIN_PEX_L4_CLKREQ_N_PD0,\n+};\n+\n+static const unsigned int pex_l4_rst_n_pd1_pins[] = {\n+\tTEGRA_PIN_PEX_L4_RST_N_PD1,\n+};\n+\n+static const unsigned int pex_l5_clkreq_n_pd2_pins[] = {\n+\tTEGRA_PIN_PEX_L5_CLKREQ_N_PD2,\n+};\n+\n+static const unsigned int pex_l5_rst_n_pd3_pins[] = {\n+\tTEGRA_PIN_PEX_L5_RST_N_PD3,\n+};\n+\n+static const unsigned int eth0_mdio_pd4_pins[] = {\n+\tTEGRA_PIN_ETH0_MDIO_PD4,\n+};\n+\n+static const unsigned int eth0_mdc_pd5_pins[] = {\n+\tTEGRA_PIN_ETH0_MDC_PD5,\n+};\n+\n+static const unsigned int eth3_mdio_pd6_pins[] = {\n+\tTEGRA_PIN_ETH3_MDIO_PD6,\n+};\n+\n+static const unsigned int eth3_mdc_pd7_pins[] = {\n+\tTEGRA_PIN_ETH3_MDC_PD7,\n+};\n+\n+static const unsigned int eth1_mdio_pe0_pins[] = {\n+\tTEGRA_PIN_ETH1_MDIO_PE0,\n+};\n+\n+static const unsigned int eth1_mdc_pe1_pins[] = {\n+\tTEGRA_PIN_ETH1_MDC_PE1,\n+};\n+\n+static const unsigned int eth2_mdio_pe2_pins[] = {\n+\tTEGRA_PIN_ETH2_MDIO_PE2,\n+};\n+\n+static const unsigned int eth2_mdc_pe3_pins[] = {\n+\tTEGRA_PIN_ETH2_MDC_PE3,\n+};\n+\n+static const unsigned int sdmmc1_clk_px0_pins[] = {\n+\tTEGRA_PIN_SDMMC1_CLK_PX0,\n+};\n+\n+static const unsigned int sdmmc1_cmd_px1_pins[] = {\n+\tTEGRA_PIN_SDMMC1_CMD_PX1,\n+};\n+\n+static const unsigned int sdmmc1_dat0_px2_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT0_PX2,\n+};\n+\n+static const unsigned int sdmmc1_dat1_px3_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT1_PX3,\n+};\n+\n+static const unsigned int sdmmc1_dat2_px4_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT2_PX4,\n+};\n+\n+static const unsigned int sdmmc1_dat3_px5_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT3_PX5,\n+};\n+\n+static const unsigned int sdmmc1_comp_pins[] = {\n+\tTEGRA_PIN_SDMMC1_COMP,\n+};\n+\n+static const unsigned int cpu_pwr_req_ph0_pins[] = {\n+\tTEGRA_PIN_CPU_PWR_REQ_PH0,\n+};\n+\n+static const unsigned int gpu_pwr_req_ph1_pins[] = {\n+\tTEGRA_PIN_GPU_PWR_REQ_PH1,\n+};\n+\n+static const unsigned int uart10_tx_ph2_pins[] = {\n+\tTEGRA_PIN_UART10_TX_PH2,\n+};\n+\n+static const unsigned int uart10_rx_ph3_pins[] = {\n+\tTEGRA_PIN_UART10_RX_PH3,\n+};\n+\n+static const unsigned int uart10_rts_n_ph4_pins[] = {\n+\tTEGRA_PIN_UART10_RTS_N_PH4,\n+};\n+\n+static const unsigned int uart10_cts_n_ph5_pins[] = {\n+\tTEGRA_PIN_UART10_CTS_N_PH5,\n+};\n+\n+static const unsigned int spi3_sck_ph6_pins[] = {\n+\tTEGRA_PIN_SPI3_SCK_PH6,\n+};\n+\n+static const unsigned int spi3_miso_ph7_pins[] = {\n+\tTEGRA_PIN_SPI3_MISO_PH7,\n+};\n+\n+static const unsigned int spi3_mosi_pj0_pins[] = {\n+\tTEGRA_PIN_SPI3_MOSI_PJ0,\n+};\n+\n+static const unsigned int spi3_cs0_pj1_pins[] = {\n+\tTEGRA_PIN_SPI3_CS0_PJ1,\n+};\n+\n+static const unsigned int spi3_cs3_pj2_pins[] = {\n+\tTEGRA_PIN_SPI3_CS3_PJ2,\n+};\n+\n+static const unsigned int uart5_tx_pj3_pins[] = {\n+\tTEGRA_PIN_UART5_TX_PJ3,\n+};\n+\n+static const unsigned int uart5_rx_pj4_pins[] = {\n+\tTEGRA_PIN_UART5_RX_PJ4,\n+};\n+\n+static const unsigned int uart5_rts_n_pj5_pins[] = {\n+\tTEGRA_PIN_UART5_RTS_N_PJ5,\n+};\n+\n+static const unsigned int uart5_cts_n_pj6_pins[] = {\n+\tTEGRA_PIN_UART5_CTS_N_PJ6,\n+};\n+\n+static const unsigned int spi1_sck_pj7_pins[] = {\n+\tTEGRA_PIN_SPI1_SCK_PJ7,\n+};\n+\n+static const unsigned int spi1_miso_pk0_pins[] = {\n+\tTEGRA_PIN_SPI1_MISO_PK0,\n+};\n+\n+static const unsigned int spi1_mosi_pk1_pins[] = {\n+\tTEGRA_PIN_SPI1_MOSI_PK1,\n+};\n+\n+static const unsigned int spi1_cs0_pk2_pins[] = {\n+\tTEGRA_PIN_SPI1_CS0_PK2,\n+};\n+\n+static const unsigned int spi1_cs1_pk3_pins[] = {\n+\tTEGRA_PIN_SPI1_CS1_PK3,\n+};\n+\n+static const unsigned int extperiph1_clk_pk4_pins[] = {\n+\tTEGRA_PIN_EXTPERIPH1_CLK_PK4,\n+};\n+\n+static const unsigned int extperiph2_clk_pk5_pins[] = {\n+\tTEGRA_PIN_EXTPERIPH2_CLK_PK5,\n+};\n+\n+static const unsigned int gen12_i2c_scl_pk6_pins[] = {\n+\tTEGRA_PIN_GEN12_I2C_SCL_PK6,\n+};\n+\n+static const unsigned int gen12_i2c_sda_pk7_pins[] = {\n+\tTEGRA_PIN_GEN12_I2C_SDA_PK7,\n+};\n+\n+static const unsigned int soc_gpio124_pl0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO124_PL0,\n+};\n+\n+static const unsigned int soc_gpio125_pl1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO125_PL1,\n+};\n+\n+static const unsigned int fan_tach0_pl2_pins[] = {\n+\tTEGRA_PIN_FAN_TACH0_PL2,\n+};\n+\n+static const unsigned int soc_gpio127_pl3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO127_PL3,\n+};\n+\n+static const unsigned int soc_gpio128_pl4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO128_PL4,\n+};\n+\n+static const unsigned int soc_gpio129_pl5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO129_PL5,\n+};\n+\n+static const unsigned int soc_gpio130_pl6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO130_PL6,\n+};\n+\n+static const unsigned int soc_gpio131_pl7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO131_PL7,\n+};\n+\n+static const unsigned int gp_pwm9_pm0_pins[] = {\n+\tTEGRA_PIN_GP_PWM9_PM0,\n+};\n+\n+static const unsigned int soc_gpio133_pm1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO133_PM1,\n+};\n+\n+static const unsigned int uart9_tx_pm2_pins[] = {\n+\tTEGRA_PIN_UART9_TX_PM2,\n+};\n+\n+static const unsigned int uart9_rx_pm3_pins[] = {\n+\tTEGRA_PIN_UART9_RX_PM3,\n+};\n+\n+static const unsigned int uart9_rts_n_pm4_pins[] = {\n+\tTEGRA_PIN_UART9_RTS_N_PM4,\n+};\n+\n+static const unsigned int uart9_cts_n_pm5_pins[] = {\n+\tTEGRA_PIN_UART9_CTS_N_PM5,\n+};\n+\n+static const unsigned int soc_gpio170_pu0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO170_PU0,\n+};\n+\n+static const unsigned int soc_gpio171_pu1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO171_PU1,\n+};\n+\n+static const unsigned int soc_gpio172_pu2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO172_PU2,\n+};\n+\n+static const unsigned int soc_gpio173_pu3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO173_PU3,\n+};\n+\n+static const unsigned int soc_gpio174_pu4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO174_PU4,\n+};\n+\n+static const unsigned int soc_gpio175_pu5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO175_PU5,\n+};\n+\n+static const unsigned int soc_gpio176_pu6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO176_PU6,\n+};\n+\n+static const unsigned int soc_gpio177_pu7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO177_PU7,\n+};\n+\n+static const unsigned int soc_gpio178_pv0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO178_PV0,\n+};\n+\n+static const unsigned int pwm10_pv1_pins[] = {\n+\tTEGRA_PIN_PWM10_PV1,\n+};\n+\n+static const unsigned int uart4_tx_pv2_pins[] = {\n+\tTEGRA_PIN_UART4_TX_PV2,\n+};\n+\n+static const unsigned int uart4_rx_pv3_pins[] = {\n+\tTEGRA_PIN_UART4_RX_PV3,\n+};\n+\n+static const unsigned int uart4_rts_n_pv4_pins[] = {\n+\tTEGRA_PIN_UART4_RTS_N_PV4,\n+};\n+\n+static const unsigned int uart4_cts_n_pv5_pins[] = {\n+\tTEGRA_PIN_UART4_CTS_N_PV5,\n+};\n+\n+static const unsigned int dap2_clk_pv6_pins[] = {\n+\tTEGRA_PIN_DAP2_CLK_PV6,\n+};\n+\n+static const unsigned int dap2_din_pv7_pins[] = {\n+\tTEGRA_PIN_DAP2_DIN_PV7,\n+};\n+\n+static const unsigned int dap2_dout_pw0_pins[] = {\n+\tTEGRA_PIN_DAP2_DOUT_PW0,\n+};\n+\n+static const unsigned int dap2_fs_pw1_pins[] = {\n+\tTEGRA_PIN_DAP2_FS_PW1,\n+};\n+\n+static const unsigned int gen1_i2c_scl_pw2_pins[] = {\n+\tTEGRA_PIN_GEN1_I2C_SCL_PW2,\n+};\n+\n+static const unsigned int gen1_i2c_sda_pw3_pins[] = {\n+\tTEGRA_PIN_GEN1_I2C_SDA_PW3,\n+};\n+\n+static const unsigned int gen0_i2c_scl_pw4_pins[] = {\n+\tTEGRA_PIN_GEN0_I2C_SCL_PW4,\n+};\n+\n+static const unsigned int gen0_i2c_sda_pw5_pins[] = {\n+\tTEGRA_PIN_GEN0_I2C_SDA_PW5,\n+};\n+\n+static const unsigned int pwr_i2c_scl_pw6_pins[] = {\n+\tTEGRA_PIN_PWR_I2C_SCL_PW6,\n+};\n+\n+static const unsigned int pwr_i2c_sda_pw7_pins[] = {\n+\tTEGRA_PIN_PWR_I2C_SDA_PW7,\n+};\n+\n+static const unsigned int qspi0_sck_pt0_pins[] = {\n+\tTEGRA_PIN_QSPI0_SCK_PT0,\n+};\n+\n+static const unsigned int qspi0_cs_n_pt1_pins[] = {\n+\tTEGRA_PIN_QSPI0_CS_N_PT1,\n+};\n+\n+static const unsigned int qspi0_io0_pt2_pins[] = {\n+\tTEGRA_PIN_QSPI0_IO0_PT2,\n+};\n+\n+static const unsigned int qspi0_io1_pt3_pins[] = {\n+\tTEGRA_PIN_QSPI0_IO1_PT3,\n+};\n+\n+static const unsigned int qspi0_io2_pt4_pins[] = {\n+\tTEGRA_PIN_QSPI0_IO2_PT4,\n+};\n+\n+static const unsigned int qspi0_io3_pt5_pins[] = {\n+\tTEGRA_PIN_QSPI0_IO3_PT5,\n+};\n+\n+static const unsigned int soc_gpio192_pt6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO192_PT6,\n+};\n+\n+static const unsigned int soc_gpio138_pp0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO138_PP0,\n+};\n+\n+static const unsigned int soc_gpio139_pp1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO139_PP1,\n+};\n+\n+static const unsigned int dap6_sclk_pp2_pins[] = {\n+\tTEGRA_PIN_DAP6_SCLK_PP2,\n+};\n+\n+static const unsigned int dap6_dout_pp3_pins[] = {\n+\tTEGRA_PIN_DAP6_DOUT_PP3,\n+};\n+\n+static const unsigned int dap6_din_pp4_pins[] = {\n+\tTEGRA_PIN_DAP6_DIN_PP4,\n+};\n+\n+static const unsigned int dap6_fs_pp5_pins[] = {\n+\tTEGRA_PIN_DAP6_FS_PP5,\n+};\n+\n+static const unsigned int dap4_sclk_pp6_pins[] = {\n+\tTEGRA_PIN_DAP4_SCLK_PP6,\n+};\n+\n+static const unsigned int dap4_dout_pp7_pins[] = {\n+\tTEGRA_PIN_DAP4_DOUT_PP7,\n+};\n+\n+static const unsigned int dap4_din_pq0_pins[] = {\n+\tTEGRA_PIN_DAP4_DIN_PQ0,\n+};\n+\n+static const unsigned int dap4_fs_pq1_pins[] = {\n+\tTEGRA_PIN_DAP4_FS_PQ1,\n+};\n+\n+static const unsigned int spi5_sck_pq2_pins[] = {\n+\tTEGRA_PIN_SPI5_SCK_PQ2,\n+};\n+\n+static const unsigned int spi5_miso_pq3_pins[] = {\n+\tTEGRA_PIN_SPI5_MISO_PQ3,\n+};\n+\n+static const unsigned int spi5_mosi_pq4_pins[] = {\n+\tTEGRA_PIN_SPI5_MOSI_PQ4,\n+};\n+\n+static const unsigned int spi5_cs0_pq5_pins[] = {\n+\tTEGRA_PIN_SPI5_CS0_PQ5,\n+};\n+\n+static const unsigned int soc_gpio152_pq6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO152_PQ6,\n+};\n+\n+static const unsigned int soc_gpio153_pq7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO153_PQ7,\n+};\n+\n+static const unsigned int aud_mclk_pr0_pins[] = {\n+\tTEGRA_PIN_AUD_MCLK_PR0,\n+};\n+\n+static const unsigned int soc_gpio155_pr1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO155_PR1,\n+};\n+\n+static const unsigned int dap1_sclk_pr2_pins[] = {\n+\tTEGRA_PIN_DAP1_SCLK_PR2,\n+};\n+\n+static const unsigned int dap1_out_pr3_pins[] = {\n+\tTEGRA_PIN_DAP1_OUT_PR3,\n+};\n+\n+static const unsigned int dap1_in_pr4_pins[] = {\n+\tTEGRA_PIN_DAP1_IN_PR4,\n+};\n+\n+static const unsigned int dap1_fs_pr5_pins[] = {\n+\tTEGRA_PIN_DAP1_FS_PR5,\n+};\n+\n+static const unsigned int gen11_i2c_scl_pr6_pins[] = {\n+\tTEGRA_PIN_GEN11_I2C_SCL_PR6,\n+};\n+\n+static const unsigned int gen11_i2c_sda_pr7_pins[] = {\n+\tTEGRA_PIN_GEN11_I2C_SDA_PR7,\n+};\n+\n+static const unsigned int soc_gpio350_ps0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO350_PS0,\n+};\n+\n+static const unsigned int soc_gpio351_ps1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO351_PS1,\n+};\n+\n+static const unsigned int soc_gpio270_py0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO270_PY0,\n+};\n+\n+static const unsigned int soc_gpio271_py1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO271_PY1,\n+};\n+\n+static const unsigned int soc_gpio272_py2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO272_PY2,\n+};\n+\n+static const unsigned int soc_gpio273_py3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO273_PY3,\n+};\n+\n+static const unsigned int soc_gpio274_py4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO274_PY4,\n+};\n+\n+static const unsigned int soc_gpio275_py5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO275_PY5,\n+};\n+\n+static const unsigned int soc_gpio276_py6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO276_PY6,\n+};\n+\n+static const unsigned int soc_gpio277_py7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO277_PY7,\n+};\n+\n+static const unsigned int soc_gpio278_pz0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO278_PZ0,\n+};\n+\n+static const unsigned int soc_gpio279_pz1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO279_PZ1,\n+};\n+\n+static const unsigned int xhalt_trig_pz2_pins[] = {\n+\tTEGRA_PIN_XHALT_TRIG_PZ2,\n+};\n+\n+static const unsigned int soc_gpio281_pz3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO281_PZ3,\n+};\n+\n+static const unsigned int soc_gpio282_pz4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO282_PZ4,\n+};\n+\n+static const unsigned int soc_gpio283_pz5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO283_PZ5,\n+};\n+\n+static const unsigned int soc_gpio284_pz6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO284_PZ6,\n+};\n+\n+static const unsigned int soc_gpio285_pz7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO285_PZ7,\n+};\n+\n+static const unsigned int soc_gpio286_pal0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO286_PAL0,\n+};\n+\n+static const unsigned int soc_gpio287_pal1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO287_PAL1,\n+};\n+\n+static const unsigned int soc_gpio288_pal2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO288_PAL2,\n+};\n+\n+static const unsigned int soc_gpio00_paa0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO00_PAA0,\n+};\n+\n+static const unsigned int vcomp_alert_paa1_pins[] = {\n+\tTEGRA_PIN_VCOMP_ALERT_PAA1,\n+};\n+\n+static const unsigned int ao_retention_n_paa2_pins[] = {\n+\tTEGRA_PIN_AO_RETENTION_N_PAA2,\n+};\n+\n+static const unsigned int batt_oc_paa3_pins[] = {\n+\tTEGRA_PIN_BATT_OC_PAA3,\n+};\n+\n+static const unsigned int bootv_ctl_n_paa4_pins[] = {\n+\tTEGRA_PIN_BOOTV_CTL_N_PAA4,\n+};\n+\n+static const unsigned int power_on_paa5_pins[] = {\n+\tTEGRA_PIN_POWER_ON_PAA5,\n+};\n+\n+static const unsigned int hdmi_cec_paa6_pins[] = {\n+\tTEGRA_PIN_HDMI_CEC_PAA6,\n+};\n+\n+static const unsigned int soc_gpio07_paa7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO07_PAA7,\n+};\n+\n+static const unsigned int soc_gpio08_pbb0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO08_PBB0,\n+};\n+\n+static const unsigned int soc_gpio09_pbb1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO09_PBB1,\n+};\n+\n+static const unsigned int gen2_i2c_scl_pcc0_pins[] = {\n+\tTEGRA_PIN_GEN2_I2C_SCL_PCC0,\n+};\n+\n+static const unsigned int gen2_i2c_sda_pcc1_pins[] = {\n+\tTEGRA_PIN_GEN2_I2C_SDA_PCC1,\n+};\n+\n+static const unsigned int gen3_i2c_scl_pcc2_pins[] = {\n+\tTEGRA_PIN_GEN3_I2C_SCL_PCC2,\n+};\n+\n+static const unsigned int gen3_i2c_sda_pcc3_pins[] = {\n+\tTEGRA_PIN_GEN3_I2C_SDA_PCC3,\n+};\n+\n+static const unsigned int gp_pwm4_pcc4_pins[] = {\n+\tTEGRA_PIN_GP_PWM4_PCC4,\n+};\n+\n+static const unsigned int uart0_tx_pcc5_pins[] = {\n+\tTEGRA_PIN_UART0_TX_PCC5,\n+};\n+\n+static const unsigned int uart0_rx_pcc6_pins[] = {\n+\tTEGRA_PIN_UART0_RX_PCC6,\n+};\n+\n+static const unsigned int spi2_sck_pcc7_pins[] = {\n+\tTEGRA_PIN_SPI2_SCK_PCC7,\n+};\n+\n+static const unsigned int spi2_miso_pdd0_pins[] = {\n+\tTEGRA_PIN_SPI2_MISO_PDD0,\n+};\n+\n+static const unsigned int spi2_mosi_pdd1_pins[] = {\n+\tTEGRA_PIN_SPI2_MOSI_PDD1,\n+};\n+\n+static const unsigned int spi2_cs0_n_pdd2_pins[] = {\n+\tTEGRA_PIN_SPI2_CS0_N_PDD2,\n+};\n+\n+static const unsigned int soc_gpio21_pdd3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO21_PDD3,\n+};\n+\n+static const unsigned int soc_gpio22_pdd4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO22_PDD4,\n+};\n+\n+static const unsigned int soc_gpio23_pdd5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO23_PDD5,\n+};\n+\n+static const unsigned int soc_gpio24_pdd6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO24_PDD6,\n+};\n+\n+static const unsigned int soc_gpio25_pdd7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO25_PDD7,\n+};\n+\n+static const unsigned int soc_gpio26_pee0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO26_PEE0,\n+};\n+\n+static const unsigned int soc_gpio27_pee1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO27_PEE1,\n+};\n+\n+static const unsigned int soc_gpio28_pee2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO28_PEE2,\n+};\n+\n+static const unsigned int soc_gpio29_pee3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO29_PEE3,\n+};\n+\n+enum tegra_mux_dt {\n+\tTEGRA_MUX_DCA_VSYNC,\n+\tTEGRA_MUX_DCA_HSYNC,\n+\tTEGRA_MUX_RSVD0,\n+\tTEGRA_MUX_DP_AUX_CH0_HPD,\n+\tTEGRA_MUX_DP_AUX_CH1_HPD,\n+\tTEGRA_MUX_DP_AUX_CH2_HPD,\n+\tTEGRA_MUX_DP_AUX_CH3_HPD,\n+\tTEGRA_MUX_GP_PWM2,\n+\tTEGRA_MUX_GP_PWM3,\n+\tTEGRA_MUX_I2C7_CLK,\n+\tTEGRA_MUX_I2C7_DAT,\n+\tTEGRA_MUX_I2C9_CLK,\n+\tTEGRA_MUX_I2C9_DAT,\n+\tTEGRA_MUX_UARTK_CTS,\n+\tTEGRA_MUX_UARTK_RTS,\n+\tTEGRA_MUX_UARTK_RXD,\n+\tTEGRA_MUX_UARTK_TXD,\n+\tTEGRA_MUX_SPI3_CS0,\n+\tTEGRA_MUX_SPI3_CS3,\n+\tTEGRA_MUX_SPI3_DIN,\n+\tTEGRA_MUX_SPI3_DOUT,\n+\tTEGRA_MUX_SPI3_SCK,\n+\tTEGRA_MUX_UARTF_CTS,\n+\tTEGRA_MUX_UARTF_RTS,\n+\tTEGRA_MUX_UARTF_RXD,\n+\tTEGRA_MUX_UARTF_TXD,\n+\tTEGRA_MUX_SPI1_CS0,\n+\tTEGRA_MUX_SPI1_CS1,\n+\tTEGRA_MUX_SPI1_DIN,\n+\tTEGRA_MUX_SPI1_DOUT,\n+\tTEGRA_MUX_SPI1_SCK,\n+\tTEGRA_MUX_EXTPERIPH2_CLK,\n+\tTEGRA_MUX_EXTPERIPH1_CLK,\n+\tTEGRA_MUX_I2C12_CLK,\n+\tTEGRA_MUX_I2C12_DAT,\n+\tTEGRA_MUX_NV_THERM_FAN_TACH0,\n+\tTEGRA_MUX_GP_PWM9,\n+\tTEGRA_MUX_UARTJ_CTS,\n+\tTEGRA_MUX_UARTJ_RTS,\n+\tTEGRA_MUX_UARTJ_RXD,\n+\tTEGRA_MUX_UARTJ_TXD,\n+\tTEGRA_MUX_I2C0_CLK,\n+\tTEGRA_MUX_I2C0_DAT,\n+\tTEGRA_MUX_I2C1_CLK,\n+\tTEGRA_MUX_I2C1_DAT,\n+\tTEGRA_MUX_I2S2_LRCK,\n+\tTEGRA_MUX_I2S2_SCLK,\n+\tTEGRA_MUX_I2S2_SDATA_OUT,\n+\tTEGRA_MUX_I2S2_SDATA_IN,\n+\tTEGRA_MUX_GP_PWM10,\n+\tTEGRA_MUX_UARTE_CTS,\n+\tTEGRA_MUX_UARTE_RTS,\n+\tTEGRA_MUX_UARTE_RXD,\n+\tTEGRA_MUX_UARTE_TXD,\n+\tTEGRA_MUX_I2C5_DAT,\n+\tTEGRA_MUX_I2C5_CLK,\n+\tTEGRA_MUX_I2S6_SDATA_IN,\n+\tTEGRA_MUX_I2S6_SDATA_OUT,\n+\tTEGRA_MUX_I2S6_LRCK,\n+\tTEGRA_MUX_I2S6_SCLK,\n+\tTEGRA_MUX_I2S4_SDATA_OUT,\n+\tTEGRA_MUX_I2S4_SCLK,\n+\tTEGRA_MUX_I2S4_SDATA_IN,\n+\tTEGRA_MUX_I2S4_LRCK,\n+\tTEGRA_MUX_SPI5_CS0,\n+\tTEGRA_MUX_SPI5_DIN,\n+\tTEGRA_MUX_SPI5_DOUT,\n+\tTEGRA_MUX_SPI5_SCK,\n+\tTEGRA_MUX_AUD_MCLK,\n+\tTEGRA_MUX_I2S1_SCLK,\n+\tTEGRA_MUX_I2S1_SDATA_IN,\n+\tTEGRA_MUX_I2S1_SDATA_OUT,\n+\tTEGRA_MUX_I2S1_LRCK,\n+\tTEGRA_MUX_I2C11_CLK,\n+\tTEGRA_MUX_I2C11_DAT,\n+\tTEGRA_MUX_XHALT_TRIG,\n+\tTEGRA_MUX_GP_PWM1,\n+\tTEGRA_MUX_GP_PWM6,\n+\tTEGRA_MUX_GP_PWM7,\n+\tTEGRA_MUX_GP_PWM8,\n+\tTEGRA_MUX_UFS0,\n+\tTEGRA_MUX_PE1_CLKREQ_L,\n+\tTEGRA_MUX_PE1_RST_L,\n+\tTEGRA_MUX_PE2_RST_L,\n+\tTEGRA_MUX_PE2_CLKREQ_L,\n+\tTEGRA_MUX_PE3_CLKREQ_L,\n+\tTEGRA_MUX_PE3_RST_L,\n+\tTEGRA_MUX_SGMII0_SMA_MDIO,\n+\tTEGRA_MUX_SGMII0_SMA_MDC,\n+\tTEGRA_MUX_USB_VBUS_EN0,\n+\tTEGRA_MUX_USB_VBUS_EN1,\n+\tTEGRA_MUX_ETH1_MDIO,\n+\tTEGRA_MUX_PE4_CLKREQ_L,\n+\tTEGRA_MUX_PE4_RST_L,\n+\tTEGRA_MUX_PE5_CLKREQ_L,\n+\tTEGRA_MUX_PE5_RST_L,\n+\tTEGRA_MUX_ETH0_MDIO,\n+\tTEGRA_MUX_ETH0_MDC,\n+\tTEGRA_MUX_ETH1_MDC,\n+\tTEGRA_MUX_ETH2_MDIO,\n+\tTEGRA_MUX_ETH2_MDC,\n+\tTEGRA_MUX_ETH3_MDIO,\n+\tTEGRA_MUX_ETH3_MDC,\n+\tTEGRA_MUX_QSPI0_CS_N,\n+\tTEGRA_MUX_QSPI0_IO0,\n+\tTEGRA_MUX_QSPI0_IO1,\n+\tTEGRA_MUX_QSPI0_IO2,\n+\tTEGRA_MUX_QSPI0_IO3,\n+\tTEGRA_MUX_QSPI0_SCK,\n+\tTEGRA_MUX_SDMMC1_CLK,\n+\tTEGRA_MUX_SDMMC1_CMD,\n+\tTEGRA_MUX_SDMMC1_COMP,\n+\tTEGRA_MUX_SDMMC1_DAT3,\n+\tTEGRA_MUX_SDMMC1_DAT2,\n+\tTEGRA_MUX_SDMMC1_DAT1,\n+\tTEGRA_MUX_SDMMC1_DAT0,\n+\tTEGRA_MUX_QSPI3_SCK,\n+\tTEGRA_MUX_QSPI3_CS0,\n+\tTEGRA_MUX_QSPI3_IO0,\n+\tTEGRA_MUX_QSPI3_IO1,\n+\tTEGRA_MUX_DCB_VSYNC,\n+\tTEGRA_MUX_DCB_HSYNC,\n+\tTEGRA_MUX_DSA_LSPII,\n+\tTEGRA_MUX_DCE_VSYNC,\n+\tTEGRA_MUX_DCE_HSYNC,\n+\tTEGRA_MUX_DCH_VSYNC,\n+\tTEGRA_MUX_DCH_HSYNC,\n+\tTEGRA_MUX_BL_EN,\n+\tTEGRA_MUX_BL_PWM_DIM0,\n+\tTEGRA_MUX_RSVD1,\n+\tTEGRA_MUX_SOC_THERM_OC3,\n+\tTEGRA_MUX_I2S5_SCLK,\n+\tTEGRA_MUX_I2S5_SDATA_IN,\n+\tTEGRA_MUX_EXTPERIPH3_CLK,\n+\tTEGRA_MUX_EXTPERIPH4_CLK,\n+\tTEGRA_MUX_I2S5_SDATA_OUT,\n+\tTEGRA_MUX_I2S5_LRCK,\n+\tTEGRA_MUX_SDMMC1_CD,\n+\tTEGRA_MUX_I2S7_SDATA_IN,\n+\tTEGRA_MUX_SPI4_SCK,\n+\tTEGRA_MUX_SPI4_DIN,\n+\tTEGRA_MUX_SPI4_DOUT,\n+\tTEGRA_MUX_SPI4_CS0,\n+\tTEGRA_MUX_SPI4_CS1,\n+\tTEGRA_MUX_GP_PWM5,\n+\tTEGRA_MUX_I2C14_CLK,\n+\tTEGRA_MUX_I2C14_DAT,\n+\tTEGRA_MUX_I2S8_SCLK,\n+\tTEGRA_MUX_I2S8_SDATA_OUT,\n+\tTEGRA_MUX_I2S8_LRCK,\n+\tTEGRA_MUX_I2S8_SDATA_IN,\n+\tTEGRA_MUX_I2C16_CLK,\n+\tTEGRA_MUX_I2C16_DAT,\n+\tTEGRA_MUX_I2S3_SCLK,\n+\tTEGRA_MUX_I2S3_SDATA_OUT,\n+\tTEGRA_MUX_I2S3_SDATA_IN,\n+\tTEGRA_MUX_I2S3_LRCK,\n+\tTEGRA_MUX_PM_TRIG1,\n+\tTEGRA_MUX_PM_TRIG0,\n+\tTEGRA_MUX_QSPI2_SCK,\n+\tTEGRA_MUX_QSPI2_CS0,\n+\tTEGRA_MUX_QSPI2_IO0,\n+\tTEGRA_MUX_QSPI2_IO1,\n+\tTEGRA_MUX_DCC_VSYNC,\n+\tTEGRA_MUX_DCC_HSYNC,\n+\tTEGRA_MUX_RSVD2,\n+\tTEGRA_MUX_DCF_VSYNC,\n+\tTEGRA_MUX_DCF_HSYNC,\n+\tTEGRA_MUX_SOUNDWIRE1_CLK,\n+\tTEGRA_MUX_SOUNDWIRE1_DAT0,\n+\tTEGRA_MUX_SOUNDWIRE1_DAT1,\n+\tTEGRA_MUX_SOUNDWIRE1_DAT2,\n+\tTEGRA_MUX_DMIC2_CLK,\n+\tTEGRA_MUX_DMIC2_DAT,\n+\tTEGRA_MUX_NV_THERM_FAN_TACH1,\n+\tTEGRA_MUX_I2C15_CLK,\n+\tTEGRA_MUX_I2C15_DAT,\n+\tTEGRA_MUX_I2S7_LRCK,\n+\tTEGRA_MUX_CCLA_LA_TRIGGER_MUX,\n+\tTEGRA_MUX_I2S7_SCLK,\n+\tTEGRA_MUX_I2S7_SDATA_OUT,\n+\tTEGRA_MUX_DMIC1_DAT,\n+\tTEGRA_MUX_DMIC1_CLK,\n+\tTEGRA_MUX_DCD_VSYNC,\n+\tTEGRA_MUX_DCD_HSYNC,\n+\tTEGRA_MUX_RSVD3,\n+\tTEGRA_MUX_DCG_VSYNC,\n+\tTEGRA_MUX_DCG_HSYNC,\n+\tTEGRA_MUX_DSPK1_CLK,\n+\tTEGRA_MUX_DSPK1_DAT,\n+\tTEGRA_MUX_SOC_THERM_OC2,\n+\tTEGRA_MUX_ISTCTRL_IST_DONE_N,\n+\tTEGRA_MUX_SOC_THERM_OC1,\n+\tTEGRA_MUX_TSC_EDGE_OUT0C,\n+\tTEGRA_MUX_TSC_EDGE_OUT0D,\n+\tTEGRA_MUX_TSC_EDGE_OUT0A,\n+\tTEGRA_MUX_TSC_EDGE_OUT0B,\n+\tTEGRA_MUX_TOUCH_CLK,\n+\tTEGRA_MUX_HDMI_CEC,\n+\tTEGRA_MUX_I2C2_CLK,\n+\tTEGRA_MUX_I2C2_DAT,\n+\tTEGRA_MUX_I2C3_CLK,\n+\tTEGRA_MUX_I2C3_DAT,\n+\tTEGRA_MUX_GP_PWM4,\n+\tTEGRA_MUX_UARTA_TXD,\n+\tTEGRA_MUX_UARTA_RXD,\n+\tTEGRA_MUX_SPI2_SCK,\n+\tTEGRA_MUX_SPI2_DIN,\n+\tTEGRA_MUX_SPI2_DOUT,\n+\tTEGRA_MUX_SPI2_CS0,\n+\tTEGRA_MUX_TSC_SYNC1,\n+\tTEGRA_MUX_TSC_EDGE_OUT3,\n+\tTEGRA_MUX_TSC_EDGE_OUT0,\n+\tTEGRA_MUX_TSC_EDGE_OUT1,\n+\tTEGRA_MUX_TSC_SYNC0,\n+\tTEGRA_MUX_SOUNDWIRE0_CLK,\n+\tTEGRA_MUX_SOUNDWIRE0_DAT0,\n+\tTEGRA_MUX_L0L1_RST_OUT_N,\n+\tTEGRA_MUX_L2_RST_OUT_N,\n+\tTEGRA_MUX_UARTL_TXD,\n+\tTEGRA_MUX_UARTL_RXD,\n+\tTEGRA_MUX_I2S9_SCLK,\n+\tTEGRA_MUX_I2S9_SDATA_OUT,\n+\tTEGRA_MUX_I2S9_SDATA_IN,\n+\tTEGRA_MUX_I2S9_LRCK,\n+\tTEGRA_MUX_DMIC5_DAT,\n+\tTEGRA_MUX_DMIC5_CLK,\n+\tTEGRA_MUX_TSC_EDGE_OUT2,\n+};\n+\n+/* Make list of each function name */\n+#define TEGRA_PIN_FUNCTION(lid) #lid\n+\n+static const char * const tegra264_functions[] = {\n+\tTEGRA_PIN_FUNCTION(dca_vsync),\n+\tTEGRA_PIN_FUNCTION(dca_hsync),\n+\tTEGRA_PIN_FUNCTION(rsvd0),\n+\tTEGRA_PIN_FUNCTION(dp_aux_ch0_hpd),\n+\tTEGRA_PIN_FUNCTION(dp_aux_ch1_hpd),\n+\tTEGRA_PIN_FUNCTION(dp_aux_ch2_hpd),\n+\tTEGRA_PIN_FUNCTION(dp_aux_ch3_hpd),\n+\tTEGRA_PIN_FUNCTION(gp_pwm2),\n+\tTEGRA_PIN_FUNCTION(gp_pwm3),\n+\tTEGRA_PIN_FUNCTION(i2c7_clk),\n+\tTEGRA_PIN_FUNCTION(i2c7_dat),\n+\tTEGRA_PIN_FUNCTION(i2c9_clk),\n+\tTEGRA_PIN_FUNCTION(i2c9_dat),\n+\tTEGRA_PIN_FUNCTION(uartk_cts),\n+\tTEGRA_PIN_FUNCTION(uartk_rts),\n+\tTEGRA_PIN_FUNCTION(uartk_rxd),\n+\tTEGRA_PIN_FUNCTION(uartk_txd),\n+\tTEGRA_PIN_FUNCTION(spi3_cs0),\n+\tTEGRA_PIN_FUNCTION(spi3_cs3),\n+\tTEGRA_PIN_FUNCTION(spi3_din),\n+\tTEGRA_PIN_FUNCTION(spi3_dout),\n+\tTEGRA_PIN_FUNCTION(spi3_sck),\n+\tTEGRA_PIN_FUNCTION(uartf_cts),\n+\tTEGRA_PIN_FUNCTION(uartf_rts),\n+\tTEGRA_PIN_FUNCTION(uartf_rxd),\n+\tTEGRA_PIN_FUNCTION(uartf_txd),\n+\tTEGRA_PIN_FUNCTION(spi1_cs0),\n+\tTEGRA_PIN_FUNCTION(spi1_cs1),\n+\tTEGRA_PIN_FUNCTION(spi1_din),\n+\tTEGRA_PIN_FUNCTION(spi1_dout),\n+\tTEGRA_PIN_FUNCTION(spi1_sck),\n+\tTEGRA_PIN_FUNCTION(extperiph2_clk),\n+\tTEGRA_PIN_FUNCTION(extperiph1_clk),\n+\tTEGRA_PIN_FUNCTION(i2c12_clk),\n+\tTEGRA_PIN_FUNCTION(i2c12_dat),\n+\tTEGRA_PIN_FUNCTION(nv_therm_fan_tach0),\n+\tTEGRA_PIN_FUNCTION(gp_pwm9),\n+\tTEGRA_PIN_FUNCTION(uartj_cts),\n+\tTEGRA_PIN_FUNCTION(uartj_rts),\n+\tTEGRA_PIN_FUNCTION(uartj_rxd),\n+\tTEGRA_PIN_FUNCTION(uartj_txd),\n+\tTEGRA_PIN_FUNCTION(i2c0_clk),\n+\tTEGRA_PIN_FUNCTION(i2c0_dat),\n+\tTEGRA_PIN_FUNCTION(i2c1_clk),\n+\tTEGRA_PIN_FUNCTION(i2c1_dat),\n+\tTEGRA_PIN_FUNCTION(i2s2_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s2_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s2_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s2_sdata_in),\n+\tTEGRA_PIN_FUNCTION(gp_pwm10),\n+\tTEGRA_PIN_FUNCTION(uarte_cts),\n+\tTEGRA_PIN_FUNCTION(uarte_rts),\n+\tTEGRA_PIN_FUNCTION(uarte_rxd),\n+\tTEGRA_PIN_FUNCTION(uarte_txd),\n+\tTEGRA_PIN_FUNCTION(i2c5_dat),\n+\tTEGRA_PIN_FUNCTION(i2c5_clk),\n+\tTEGRA_PIN_FUNCTION(i2s6_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s6_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s6_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s6_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s4_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s4_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s4_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s4_lrck),\n+\tTEGRA_PIN_FUNCTION(spi5_cs0),\n+\tTEGRA_PIN_FUNCTION(spi5_din),\n+\tTEGRA_PIN_FUNCTION(spi5_dout),\n+\tTEGRA_PIN_FUNCTION(spi5_sck),\n+\tTEGRA_PIN_FUNCTION(aud_mclk),\n+\tTEGRA_PIN_FUNCTION(i2s1_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s1_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s1_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s1_lrck),\n+\tTEGRA_PIN_FUNCTION(i2c11_clk),\n+\tTEGRA_PIN_FUNCTION(i2c11_dat),\n+\tTEGRA_PIN_FUNCTION(xhalt_trig),\n+\tTEGRA_PIN_FUNCTION(gp_pwm1),\n+\tTEGRA_PIN_FUNCTION(gp_pwm6),\n+\tTEGRA_PIN_FUNCTION(gp_pwm7),\n+\tTEGRA_PIN_FUNCTION(gp_pwm8),\n+\tTEGRA_PIN_FUNCTION(ufs0),\n+\tTEGRA_PIN_FUNCTION(pe1_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe1_rst_l),\n+\tTEGRA_PIN_FUNCTION(pe2_rst_l),\n+\tTEGRA_PIN_FUNCTION(pe2_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe3_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe3_rst_l),\n+\tTEGRA_PIN_FUNCTION(sgmii0_sma_mdio),\n+\tTEGRA_PIN_FUNCTION(sgmii0_sma_mdc),\n+\tTEGRA_PIN_FUNCTION(usb_vbus_en0),\n+\tTEGRA_PIN_FUNCTION(usb_vbus_en1),\n+\tTEGRA_PIN_FUNCTION(eth1_mdio),\n+\tTEGRA_PIN_FUNCTION(pe4_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe4_rst_l),\n+\tTEGRA_PIN_FUNCTION(pe5_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe5_rst_l),\n+\tTEGRA_PIN_FUNCTION(eth0_mdio),\n+\tTEGRA_PIN_FUNCTION(eth0_mdc),\n+\tTEGRA_PIN_FUNCTION(eth1_mdc),\n+\tTEGRA_PIN_FUNCTION(eth2_mdio),\n+\tTEGRA_PIN_FUNCTION(eth2_mdc),\n+\tTEGRA_PIN_FUNCTION(eth3_mdio),\n+\tTEGRA_PIN_FUNCTION(eth3_mdc),\n+\tTEGRA_PIN_FUNCTION(qspi0_cs_n),\n+\tTEGRA_PIN_FUNCTION(qspi0_io0),\n+\tTEGRA_PIN_FUNCTION(qspi0_io1),\n+\tTEGRA_PIN_FUNCTION(qspi0_io2),\n+\tTEGRA_PIN_FUNCTION(qspi0_io3),\n+\tTEGRA_PIN_FUNCTION(qspi0_sck),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_clk),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_cmd),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_comp),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat3),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat2),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat1),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat0),\n+\tTEGRA_PIN_FUNCTION(qspi3_sck),\n+\tTEGRA_PIN_FUNCTION(qspi3_cs0),\n+\tTEGRA_PIN_FUNCTION(qspi3_io0),\n+\tTEGRA_PIN_FUNCTION(qspi3_io1),\n+\tTEGRA_PIN_FUNCTION(dcb_vsync),\n+\tTEGRA_PIN_FUNCTION(dcb_hsync),\n+\tTEGRA_PIN_FUNCTION(dsa_lspii),\n+\tTEGRA_PIN_FUNCTION(dce_vsync),\n+\tTEGRA_PIN_FUNCTION(dce_hsync),\n+\tTEGRA_PIN_FUNCTION(dch_vsync),\n+\tTEGRA_PIN_FUNCTION(dch_hsync),\n+\tTEGRA_PIN_FUNCTION(bl_en),\n+\tTEGRA_PIN_FUNCTION(bl_pwm_dim0),\n+\tTEGRA_PIN_FUNCTION(rsvd1),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc3),\n+\tTEGRA_PIN_FUNCTION(i2s5_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s5_sdata_in),\n+\tTEGRA_PIN_FUNCTION(extperiph3_clk),\n+\tTEGRA_PIN_FUNCTION(extperiph4_clk),\n+\tTEGRA_PIN_FUNCTION(i2s5_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s5_lrck),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_cd),\n+\tTEGRA_PIN_FUNCTION(i2s7_sdata_in),\n+\tTEGRA_PIN_FUNCTION(spi4_sck),\n+\tTEGRA_PIN_FUNCTION(spi4_din),\n+\tTEGRA_PIN_FUNCTION(spi4_dout),\n+\tTEGRA_PIN_FUNCTION(spi4_cs0),\n+\tTEGRA_PIN_FUNCTION(spi4_cs1),\n+\tTEGRA_PIN_FUNCTION(gp_pwm5),\n+\tTEGRA_PIN_FUNCTION(i2c14_clk),\n+\tTEGRA_PIN_FUNCTION(i2c14_dat),\n+\tTEGRA_PIN_FUNCTION(i2s8_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s8_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s8_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s8_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2c16_clk),\n+\tTEGRA_PIN_FUNCTION(i2c16_dat),\n+\tTEGRA_PIN_FUNCTION(i2s3_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s3_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s3_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s3_lrck),\n+\tTEGRA_PIN_FUNCTION(pm_trig1),\n+\tTEGRA_PIN_FUNCTION(pm_trig0),\n+\tTEGRA_PIN_FUNCTION(qspi2_sck),\n+\tTEGRA_PIN_FUNCTION(qspi2_cs0),\n+\tTEGRA_PIN_FUNCTION(qspi2_io0),\n+\tTEGRA_PIN_FUNCTION(qspi2_io1),\n+\tTEGRA_PIN_FUNCTION(dcc_vsync),\n+\tTEGRA_PIN_FUNCTION(dcc_hsync),\n+\tTEGRA_PIN_FUNCTION(rsvd2),\n+\tTEGRA_PIN_FUNCTION(dcf_vsync),\n+\tTEGRA_PIN_FUNCTION(dcf_hsync),\n+\tTEGRA_PIN_FUNCTION(soundwire1_clk),\n+\tTEGRA_PIN_FUNCTION(soundwire1_dat0),\n+\tTEGRA_PIN_FUNCTION(soundwire1_dat1),\n+\tTEGRA_PIN_FUNCTION(soundwire1_dat2),\n+\tTEGRA_PIN_FUNCTION(dmic2_clk),\n+\tTEGRA_PIN_FUNCTION(dmic2_dat),\n+\tTEGRA_PIN_FUNCTION(nv_therm_fan_tach1),\n+\tTEGRA_PIN_FUNCTION(i2c15_clk),\n+\tTEGRA_PIN_FUNCTION(i2c15_dat),\n+\tTEGRA_PIN_FUNCTION(i2s7_lrck),\n+\tTEGRA_PIN_FUNCTION(ccla_la_trigger_mux),\n+\tTEGRA_PIN_FUNCTION(i2s7_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s7_sdata_out),\n+\tTEGRA_PIN_FUNCTION(dmic1_dat),\n+\tTEGRA_PIN_FUNCTION(dmic1_clk),\n+\tTEGRA_PIN_FUNCTION(dcd_vsync),\n+\tTEGRA_PIN_FUNCTION(dcd_hsync),\n+\tTEGRA_PIN_FUNCTION(rsvd3),\n+\tTEGRA_PIN_FUNCTION(dcg_vsync),\n+\tTEGRA_PIN_FUNCTION(dcg_hsync),\n+\tTEGRA_PIN_FUNCTION(dspk1_clk),\n+\tTEGRA_PIN_FUNCTION(dspk1_dat),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc2),\n+\tTEGRA_PIN_FUNCTION(istctrl_ist_done_n),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc1),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0c),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0d),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0a),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0b),\n+\tTEGRA_PIN_FUNCTION(touch_clk),\n+\tTEGRA_PIN_FUNCTION(hdmi_cec),\n+\tTEGRA_PIN_FUNCTION(i2c2_clk),\n+\tTEGRA_PIN_FUNCTION(i2c2_dat),\n+\tTEGRA_PIN_FUNCTION(i2c3_clk),\n+\tTEGRA_PIN_FUNCTION(i2c3_dat),\n+\tTEGRA_PIN_FUNCTION(gp_pwm4),\n+\tTEGRA_PIN_FUNCTION(uarta_txd),\n+\tTEGRA_PIN_FUNCTION(uarta_rxd),\n+\tTEGRA_PIN_FUNCTION(spi2_sck),\n+\tTEGRA_PIN_FUNCTION(spi2_din),\n+\tTEGRA_PIN_FUNCTION(spi2_dout),\n+\tTEGRA_PIN_FUNCTION(spi2_cs0),\n+\tTEGRA_PIN_FUNCTION(tsc_sync1),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out3),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out1),\n+\tTEGRA_PIN_FUNCTION(tsc_sync0),\n+\tTEGRA_PIN_FUNCTION(soundwire0_clk),\n+\tTEGRA_PIN_FUNCTION(soundwire0_dat0),\n+\tTEGRA_PIN_FUNCTION(l0l1_rst_out_n),\n+\tTEGRA_PIN_FUNCTION(l2_rst_out_n),\n+\tTEGRA_PIN_FUNCTION(uartl_txd),\n+\tTEGRA_PIN_FUNCTION(uartl_rxd),\n+\tTEGRA_PIN_FUNCTION(i2s9_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s9_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s9_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s9_lrck),\n+\tTEGRA_PIN_FUNCTION(dmic5_dat),\n+\tTEGRA_PIN_FUNCTION(dmic5_clk),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out2),\n+};\n+\n+#define PINGROUP_REG_Y(r) ((r))\n+#define PINGROUP_REG_N(r) -1\n+\n+#define DRV_PINGROUP_Y(r) ((r))\n+\n+#define DRV_PINGROUP_ENTRY_N\t\t\t\t\t\\\n+\t\t.drv_reg = -1,\t\t\t\t\t\\\n+\t\t.drv_bank = -1,\t\t\t\t\t\\\n+\t\t.drvdn_bit = -1,\t\t\t\t\\\n+\t\t.drvup_bit = -1,\t\t\t\t\\\n+\t\t.slwr_bit = -1,\t\t\t\t\t\\\n+\t\t.slwf_bit = -1\n+\n+#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,\t\\\n+\t\t\t drvup_w, slwr_b, slwr_w, slwf_b,\t\\\n+\t\t\t slwf_w, bank)\t\t\t\\\n+\t\t.drv_reg = DRV_PINGROUP_Y(r),\t\t\t\\\n+\t\t.drv_bank = bank,\t\t\t\t\\\n+\t\t.drvdn_bit = drvdn_b,\t\t\t\t\\\n+\t\t.drvdn_width = drvdn_w,\t\t\t\t\\\n+\t\t.drvup_bit = drvup_b,\t\t\t\t\\\n+\t\t.drvup_width = drvup_w,\t\t\t\t\\\n+\t\t.slwr_bit = slwr_b,\t\t\t\t\\\n+\t\t.slwr_width = slwr_w,\t\t\t\t\\\n+\t\t.slwf_bit = slwf_b,\t\t\t\t\\\n+\t\t.slwf_width = slwf_w\n+\n+#define PIN_PINGROUP_ENTRY_N\t\t\t\t\t\\\n+\t\t.mux_reg = -1,\t\t\t\t\t\\\n+\t\t.pupd_reg = -1,\t\t\t\t\t\\\n+\t\t.tri_reg = -1,\t\t\t\t\t\\\n+\t\t.einput_bit = -1,\t\t\t\t\\\n+\t\t.e_io_hv_bit = -1,\t\t\t\t\\\n+\t\t.odrain_bit = -1,\t\t\t\t\\\n+\t\t.lock_bit = -1,\t\t\t\t\t\\\n+\t\t.parked_bit = -1,\t\t\t\t\\\n+\t\t.lpmd_bit = -1,\t\t\t\t\t\\\n+\t\t.drvtype_bit = -1,\t\t\t\t\\\n+\t\t.lpdr_bit = -1,\t\t\t\t\t\\\n+\t\t.pbias_buf_bit = -1,\t\t\t\t\\\n+\t\t.preemp_bit = -1,\t\t\t\t\\\n+\t\t.rfu_in_bit = -1\n+\n+#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input,\t\\\n+\t\t\t\te_lpdr, e_pbias_buf, gpio_sfio_sel,\t\\\n+\t\t\t\tschmitt_b)\t\t\t\t\\\n+\t\t.mux_reg = PINGROUP_REG_Y(r),\t\t\t\\\n+\t\t.lpmd_bit = -1,\t\t\t\t\t\\\n+\t\t.lock_bit = -1,\t\t\t\t\t\\\n+\t\t.hsm_bit = -1,\t\t\t\t\t\\\n+\t\t.mux_bank = bank,\t\t\t\t\\\n+\t\t.mux_bit = 0,\t\t\t\t\t\\\n+\t\t.pupd_reg = PINGROUP_REG_##pupd(r),\t\t\\\n+\t\t.pupd_bank = bank,\t\t\t\t\\\n+\t\t.pupd_bit = 2,\t\t\t\t\t\\\n+\t\t.tri_reg = PINGROUP_REG_Y(r),\t\t\t\\\n+\t\t.tri_bank = bank,\t\t\t\t\\\n+\t\t.tri_bit = 4,\t\t\t\t\t\\\n+\t\t.einput_bit = e_input,\t\t\t\t\\\n+\t\t.sfsel_bit = gpio_sfio_sel,\t\t\t\\\n+\t\t.schmitt_bit = schmitt_b,\t\t\t\\\n+\t\t.drvtype_bit = 13,\t\t\t\t\\\n+\t\t.lpdr_bit = e_lpdr,\n+\n+#define drive_eth1_mdio_pe0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l4_clkreq_n_pd0 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l4_rst_n_pd1 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l5_clkreq_n_pd2 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l5_rst_n_pd3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth0_mdio_pd4 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth0_mdc_pd5 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth1_mdc_pe1 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth2_mdio_pe2 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth2_mdc_pe3 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth3_mdio_pd6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_eth3_mdc_pd7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l1_clkreq_n_pb0 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l1_rst_n_pb1 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_wake_n_pc2 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l2_rst_n_pb3 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l2_clkreq_n_pb2 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l3_clkreq_n_pb4 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pex_l3_rst_n_pb5 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_sgmii0_sma_mdio_pc0 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_sgmii0_sma_mdc_pc1 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio113_pb6 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio114_pb7 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm1_pa0 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm6_pa1 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm7_pa2 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm8_pa3 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_ufs0_ref_clk_pa4 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_ufs0_rst_n_pa5 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+\n+#define drive_cpu_pwr_req_ph0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gpu_pwr_req_ph1 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart10_cts_n_ph5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart10_rts_n_ph4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart10_rx_ph3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart10_tx_ph2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi3_cs0_pj1 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi3_cs3_pj2 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi3_miso_ph7 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi3_mosi_pj0 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi3_sck_ph6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart5_cts_n_pj6 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart5_rts_n_pj5 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart5_rx_pj4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart5_tx_pj3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi1_cs0_pk2 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi1_cs1_pk3 DRV_PINGROUP_ENTRY_Y(0x84, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi1_miso_pk0 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi1_mosi_pk1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi1_sck_pj7 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_extperiph2_clk_pk5 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_extperiph1_clk_pk4 DRV_PINGROUP_ENTRY_Y(0xac, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen12_i2c_scl_pk6 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen12_i2c_sda_pk7 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio124_pl0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio125_pl1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_fan_tach0_pl2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio127_pl3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio128_pl4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio129_pl5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio130_pl6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio131_pl7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gp_pwm9_pm0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio133_pm1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart9_cts_n_pm5 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart9_rts_n_pm4 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart9_rx_pm3 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart9_tx_pm2 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N\n+#define drive_sdmmc1_clk_px0 DRV_PINGROUP_ENTRY_Y(0x2004, 28, 2, 30, 2, -1, -1, -1, -1, 0)\n+#define drive_sdmmc1_cmd_px1 DRV_PINGROUP_ENTRY_Y(0x200c, 28, 2, 30, 2, -1, -1, -1, -1, 0)\n+#define drive_sdmmc1_dat3_px5 DRV_PINGROUP_ENTRY_Y(0x201c, 28, 2, 30, 2, -1, -1, -1, -1, 0)\n+#define drive_sdmmc1_dat2_px4 DRV_PINGROUP_ENTRY_Y(0x2024, 28, 2, 30, 2, -1, -1, -1, -1, 0)\n+#define drive_sdmmc1_dat1_px3 DRV_PINGROUP_ENTRY_Y(0x202c, 28, 2, 30, 2, -1, -1, -1, -1, 0)\n+#define drive_sdmmc1_dat0_px2 DRV_PINGROUP_ENTRY_Y(0x2034, 28, 2, 30, 2, -1, -1, -1, -1, 0)\n+#define drive_qspi0_cs_n_pt1 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_qspi0_io0_pt2 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_qspi0_io1_pt3 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_qspi0_io2_pt4 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_qspi0_io3_pt5 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_qspi0_sck_pt0 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio192_pt6 DRV_PINGROUP_ENTRY_Y(0x3034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio138_pp0 DRV_PINGROUP_ENTRY_Y(0x5004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio139_pp1 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap6_din_pp4 DRV_PINGROUP_ENTRY_Y(0x5014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap6_dout_pp3 DRV_PINGROUP_ENTRY_Y(0x501c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap6_fs_pp5 DRV_PINGROUP_ENTRY_Y(0x5024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap6_sclk_pp2 DRV_PINGROUP_ENTRY_Y(0x502c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap4_dout_pp7 DRV_PINGROUP_ENTRY_Y(0x5034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap4_sclk_pp6 DRV_PINGROUP_ENTRY_Y(0x503c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap4_din_pq0 DRV_PINGROUP_ENTRY_Y(0x5044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap4_fs_pq1 DRV_PINGROUP_ENTRY_Y(0x504c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi5_cs0_pq5 DRV_PINGROUP_ENTRY_Y(0x5054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi5_miso_pq3 DRV_PINGROUP_ENTRY_Y(0x505c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi5_mosi_pq4 DRV_PINGROUP_ENTRY_Y(0x5064, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi5_sck_pq2 DRV_PINGROUP_ENTRY_Y(0x506c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio152_pq6 DRV_PINGROUP_ENTRY_Y(0x5074, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio153_pq7 DRV_PINGROUP_ENTRY_Y(0x507c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio155_pr1 DRV_PINGROUP_ENTRY_Y(0x5084, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_aud_mclk_pr0 DRV_PINGROUP_ENTRY_Y(0x508c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap1_sclk_pr2 DRV_PINGROUP_ENTRY_Y(0x5094, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap1_in_pr4 DRV_PINGROUP_ENTRY_Y(0x509c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap1_out_pr3 DRV_PINGROUP_ENTRY_Y(0x50a4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap1_fs_pr5 DRV_PINGROUP_ENTRY_Y(0x50ac, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen11_i2c_scl_pr6 DRV_PINGROUP_ENTRY_Y(0x50b4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen11_i2c_sda_pr7 DRV_PINGROUP_ENTRY_Y(0x50bc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio350_ps0 DRV_PINGROUP_ENTRY_Y(0x50c4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio351_ps1 DRV_PINGROUP_ENTRY_Y(0x50cc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen0_i2c_scl_pw4 DRV_PINGROUP_ENTRY_Y(0x6004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen0_i2c_sda_pw5 DRV_PINGROUP_ENTRY_Y(0x600c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen1_i2c_scl_pw2 DRV_PINGROUP_ENTRY_Y(0x6014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap2_din_pv7 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dap2_dout_pw0 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio172_pu2 DRV_PINGROUP_ENTRY_Y(0x607c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio173_pu3 DRV_PINGROUP_ENTRY_Y(0x6084, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio174_pu4 DRV_PINGROUP_ENTRY_Y(0x608c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio175_pu5 DRV_PINGROUP_ENTRY_Y(0x6094, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio176_pu6 DRV_PINGROUP_ENTRY_Y(0x609c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio177_pu7 DRV_PINGROUP_ENTRY_Y(0x60a4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio178_pv0 DRV_PINGROUP_ENTRY_Y(0x60ac, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart4_cts_n_pv5 DRV_PINGROUP_ENTRY_Y(0x60b4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart4_rts_n_pv4 DRV_PINGROUP_ENTRY_Y(0x60bc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart4_rx_pv3 DRV_PINGROUP_ENTRY_Y(0x60c4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart4_tx_pv2 DRV_PINGROUP_ENTRY_Y(0x60cc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwr_i2c_sda_pw7 DRV_PINGROUP_ENTRY_Y(0x60d4, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwr_i2c_scl_pw6 DRV_PINGROUP_ENTRY_Y(0x60dc, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio250_pf0 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio251_pf1 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio252_pf2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dp_aux_ch0_hpd_pf3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dp_aux_ch1_hpd_pf4 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dp_aux_ch2_hpd_pf5 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_dp_aux_ch3_hpd_pf6 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm2_pf7 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_pwm3_pg0 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen7_i2c_scl_pg1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen7_i2c_sda_pg2 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen9_i2c_scl_pg3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen9_i2c_sda_pg4 DRV_PINGROUP_ENTRY_Y(0x7064, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio270_py0 DRV_PINGROUP_ENTRY_Y(0xa004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio271_py1 DRV_PINGROUP_ENTRY_Y(0xa00c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio272_py2 DRV_PINGROUP_ENTRY_Y(0xa014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio273_py3 DRV_PINGROUP_ENTRY_Y(0xa01c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio274_py4 DRV_PINGROUP_ENTRY_Y(0xa024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio275_py5 DRV_PINGROUP_ENTRY_Y(0xa02c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio276_py6 DRV_PINGROUP_ENTRY_Y(0xa034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio277_py7 DRV_PINGROUP_ENTRY_Y(0xa03c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio278_pz0 DRV_PINGROUP_ENTRY_Y(0xa044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio279_pz1 DRV_PINGROUP_ENTRY_Y(0xa04c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio282_pz4 DRV_PINGROUP_ENTRY_Y(0xa054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio283_pz5 DRV_PINGROUP_ENTRY_Y(0xa05c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio284_pz6 DRV_PINGROUP_ENTRY_Y(0xa064, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio285_pz7 DRV_PINGROUP_ENTRY_Y(0xa06c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio286_pal0 DRV_PINGROUP_ENTRY_Y(0xa074, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio287_pal1 DRV_PINGROUP_ENTRY_Y(0xa07c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio288_pal2 DRV_PINGROUP_ENTRY_Y(0xa084, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_xhalt_trig_pz2 DRV_PINGROUP_ENTRY_Y(0xa08c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio281_pz3 DRV_PINGROUP_ENTRY_Y(0xa094, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+\n+#define drive_ao_retention_n_paa2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_batt_oc_paa3 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_power_on_paa5 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_vcomp_alert_paa1 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_bootv_ctl_n_paa4 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio00_paa0 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio07_paa7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio08_pbb0 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio09_pbb1 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_hdmi_cec_paa6 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen2_i2c_scl_pcc0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen2_i2c_sda_pcc1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen3_i2c_scl_pcc2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gen3_i2c_sda_pcc3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_gp_pwm4_pcc4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart0_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_uart0_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi2_sck_pcc7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi2_miso_pdd0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi2_mosi_pdd1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_spi2_cs0_n_pdd2 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio21_pdd3 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio22_pdd4 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio23_pdd5 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio24_pdd6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio25_pdd7 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio26_pee0 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio27_pee1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 4, 20, 4, -1, -1, -1, -1, 0)\n+#define drive_soc_gpio28_pee2 DRV_PINGROUP_ENTRY_N\n+#define drive_soc_gpio29_pee3 DRV_PINGROUP_ENTRY_N\n+\n+#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf,\t\\\n+\t\t\tgpio_sfio_sel, schmitt_b)\t\t\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.name = #pg_name,\t\t\t\t\t\\\n+\t\t.pins = pg_name##_pins,\t\t\t\t\t\\\n+\t\t.npins = ARRAY_SIZE(pg_name##_pins),\t\t\t\\\n+\t\t\t.funcs = {\t\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f0,\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f1,\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f2,\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f3,\t\t\t\t\\\n+\t\t\t},\t\t\t\t\t\t\\\n+\t\tPIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk,\t\\\n+\t\t\t\t\te_input, e_lpdr, e_pbias_buf,\t\\\n+\t\t\t\t\tgpio_sfio_sel, schmitt_b)\t\\\n+\t\tdrive_##pg_name,\t\t\t\t\t\\\n+\t}\n+\n+static const struct tegra_pingroup tegra264_uphy_groups[] = {\n+\tPINGROUP(eth1_mdio_pe0, ETH1_MDIO, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l4_clkreq_n_pd0, PE4_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l4_rst_n_pd1, PE4_RST_L, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l5_clkreq_n_pd2, PE5_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l5_rst_n_pd3, PE5_RST_L, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth0_mdio_pd4, ETH0_MDIO, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth0_mdc_pd5, ETH0_MDC, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth1_mdc_pe1, ETH1_MDC, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth2_mdio_pe2, ETH2_MDIO, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth2_mdc_pe3, ETH2_MDC, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth3_mdio_pd6, ETH3_MDIO, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(eth3_mdc_pd7, ETH3_MDC, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l1_clkreq_n_pb0, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l1_rst_n_pb1, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_wake_n_pc2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l2_rst_n_pb3, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l2_clkreq_n_pb2, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l3_clkreq_n_pb4, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pex_l3_rst_n_pb5, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(sgmii0_sma_mdio_pc0, SGMII0_SMA_MDIO, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(sgmii0_sma_mdc_pc1, SGMII0_SMA_MDC, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio113_pb6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio114_pb7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm1_pa0, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm6_pa1, GP_PWM6, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm7_pa2, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm8_pa3, GP_PWM8, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(ufs0_ref_clk_pa4, UFS0, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(ufs0_rst_n_pa5, UFS0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+};\n+\n+static const struct tegra_pingroup tegra264_main_groups[] = {\n+\tPINGROUP(cpu_pwr_req_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gpu_pwr_req_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart10_cts_n_ph5, UARTK_CTS, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart10_rts_n_ph4, UARTK_RTS, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart10_rx_ph3, UARTK_RXD, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart10_tx_ph2, UARTK_TXD, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi3_cs0_pj1, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi3_cs3_pj2, SPI3_CS3, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi3_miso_ph7, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi3_mosi_pj0, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi3_sck_ph6, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart5_cts_n_pj6, UARTF_CTS, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart5_rts_n_pj5, UARTF_RTS, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart5_rx_pj4, UARTF_RXD, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart5_tx_pj3, UARTF_TXD, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi1_cs0_pk2, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0x78, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi1_cs1_pk3, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0x80, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi1_miso_pk0, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0x88, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi1_mosi_pk1, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0x90, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi1_sck_pj7, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0x98, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(extperiph2_clk_pk5, EXTPERIPH2_CLK, RSVD1, DMIC2_CLK, DSPK1_CLK, 0xa0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(extperiph1_clk_pk4, EXTPERIPH1_CLK, RSVD1, DMIC2_DAT, DSPK1_DAT, 0xa8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen12_i2c_scl_pk6, I2C12_CLK, RSVD1, RSVD2, RSVD3, 0xb0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen12_i2c_sda_pk7, I2C12_DAT, RSVD1, RSVD2, RSVD3, 0xb8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio124_pl0, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio125_pl1, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(fan_tach0_pl2, NV_THERM_FAN_TACH0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio127_pl3, RSVD0, RSVD1, NV_THERM_FAN_TACH1, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio128_pl4, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio129_pl5, RSVD0, EXTPERIPH3_CLK, I2C15_CLK, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio130_pl6, RSVD0, EXTPERIPH4_CLK, I2C15_DAT, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio131_pl7, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gp_pwm9_pm0, GP_PWM9, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio133_pm1, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart9_cts_n_pm5, UARTJ_CTS, RSVD1, RSVD2, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart9_rts_n_pm4, UARTJ_RTS, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart9_rx_pm3, UARTJ_RXD, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart9_tx_pm2, UARTJ_TXD, RSVD1, RSVD2, RSVD3, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(sdmmc1_clk_px0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 5, 6, 13, -1, 10, -1),\n+\tPINGROUP(sdmmc1_cmd_px1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 5, 6, 13, -1, 10, -1),\n+\tPINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x2010, 0, N, -1, -1, -1, -1, -1, -1, -1),\n+\tPINGROUP(sdmmc1_dat3_px5, SDMMC1_DAT3, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 5, 6, 13, -1, 10, -1),\n+\tPINGROUP(sdmmc1_dat2_px4, SDMMC1_DAT2, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, 5, 6, 13, -1, 10, -1),\n+\tPINGROUP(sdmmc1_dat1_px3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, -1, 5, 6, 13, -1, 10, -1),\n+\tPINGROUP(sdmmc1_dat0_px2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, 5, 6, 13, -1, 10, -1),\n+\tPINGROUP(qspi0_cs_n_pt1, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(qspi0_io0_pt2, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(qspi0_io1_pt3, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(qspi0_io2_pt4, QSPI0_IO2, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(qspi0_io3_pt5, QSPI0_IO3, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(qspi0_sck_pt0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio192_pt6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio138_pp0, RSVD0, I2C14_CLK, DMIC1_DAT, RSVD3, 0x5000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio139_pp1, RSVD0, I2C14_DAT, DMIC1_CLK, RSVD3, 0x5008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap6_din_pp4, I2S6_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap6_dout_pp3, I2S6_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap6_fs_pp5, I2S6_LRCK, RSVD1, RSVD2, RSVD3, 0x5020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap6_sclk_pp2, I2S6_SCLK, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap4_dout_pp7, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap4_sclk_pp6, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap4_din_pq0, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap4_fs_pq1, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi5_cs0_pq5, SPI5_CS0, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi5_miso_pq3, SPI5_DIN, RSVD1, RSVD2, RSVD3, 0x5058, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi5_mosi_pq4, SPI5_DOUT, RSVD1, RSVD2, RSVD3, 0x5060, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi5_sck_pq2, SPI5_SCK, RSVD1, RSVD2, RSVD3, 0x5068, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio152_pq6, RSVD0, I2S8_SCLK, RSVD2, RSVD3, 0x5070, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio153_pq7, RSVD0, I2S8_SDATA_OUT, RSVD2, RSVD3, 0x5078, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio155_pr1, RSVD0, I2S8_LRCK, RSVD2, RSVD3, 0x5080, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(aud_mclk_pr0, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x5088, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap1_sclk_pr2, I2S1_SCLK, RSVD1, RSVD2, RSVD3, 0x5090, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap1_in_pr4, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5098, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap1_out_pr3, I2S1_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x50a0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap1_fs_pr5, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x50a8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen11_i2c_scl_pr6, I2C11_CLK, RSVD1, RSVD2, RSVD3, 0x50b0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen11_i2c_sda_pr7, I2C11_DAT, RSVD1, RSVD2, RSVD3, 0x50b8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio350_ps0, RSVD0, I2S8_SDATA_IN, RSVD2, RSVD3, 0x50c0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio351_ps1, RSVD0, RSVD1, RSVD2, RSVD3, 0x50c8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen0_i2c_scl_pw4, I2C0_CLK, RSVD1, RSVD2, RSVD3, 0x6000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen0_i2c_sda_pw5, I2C0_DAT, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen1_i2c_scl_pw2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio172_pu2, RSVD0, SPI4_DIN, RSVD2, RSVD3, 0x6078, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio173_pu3, RSVD0, SPI4_DOUT, RSVD2, RSVD3, 0x6080, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio174_pu4, RSVD0, SPI4_CS0, RSVD2, RSVD3, 0x6088, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio175_pu5, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x6090, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio176_pu6, RSVD0, RSVD1, I2S7_SCLK, RSVD3, 0x6098, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio177_pu7, RSVD0, GP_PWM5, RSVD2, RSVD3, 0x60a0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio178_pv0, RSVD0, RSVD1, I2S7_SDATA_OUT, RSVD3, 0x60a8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart4_cts_n_pv5, UARTE_CTS, RSVD1, RSVD2, RSVD3, 0x60b0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart4_rts_n_pv4, UARTE_RTS, RSVD1, RSVD2, RSVD3, 0x60b8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart4_rx_pv3, UARTE_RXD, RSVD1, RSVD2, RSVD3, 0x60c0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart4_tx_pv2, UARTE_TXD, RSVD1, RSVD2, RSVD3, 0x60c8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwr_i2c_sda_pw7, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x60d0, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwr_i2c_scl_pw6, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x60d8, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio250_pf0, DCA_VSYNC, DCB_VSYNC, DCC_VSYNC, DCD_VSYNC, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio251_pf1, DCA_HSYNC, DCB_HSYNC, DCC_HSYNC, DCD_HSYNC, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio252_pf2, RSVD0, DSA_LSPII, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dp_aux_ch0_hpd_pf3, DP_AUX_CH0_HPD, DCE_VSYNC, DCF_VSYNC, DCG_VSYNC, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dp_aux_ch1_hpd_pf4, DP_AUX_CH1_HPD, DCE_HSYNC, DCF_HSYNC, DCG_HSYNC, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dp_aux_ch2_hpd_pf5, DP_AUX_CH2_HPD, DCH_VSYNC, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(dp_aux_ch3_hpd_pf6, DP_AUX_CH3_HPD, DCH_HSYNC, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm2_pf7, GP_PWM2, BL_EN, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(pwm3_pg0, GP_PWM3, BL_PWM_DIM0, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen7_i2c_scl_pg1, I2C7_CLK, RSVD1, SOUNDWIRE1_CLK, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen7_i2c_sda_pg2, I2C7_DAT, RSVD1, SOUNDWIRE1_DAT0, RSVD3, 0x7050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen9_i2c_scl_pg3, I2C9_CLK, RSVD1, SOUNDWIRE1_DAT1, RSVD3, 0x7058, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen9_i2c_sda_pg4, I2C9_DAT, RSVD1, SOUNDWIRE1_DAT2, RSVD3, 0x7060, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio270_py0, RSVD0, I2C16_CLK, RSVD2, RSVD3, 0xa000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio271_py1, RSVD0, I2C16_DAT, RSVD2, RSVD3, 0xa008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio272_py2, RSVD0, I2S3_SCLK, RSVD2, RSVD3, 0xa010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio273_py3, RSVD0, I2S3_SDATA_OUT, RSVD2, RSVD3, 0xa018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio274_py4, RSVD0, I2S3_SDATA_IN, RSVD2, RSVD3, 0xa020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio275_py5, RSVD0, I2S3_LRCK, RSVD2, RSVD3, 0xa028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio276_py6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio277_py7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa038, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio278_pz0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio279_pz1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio282_pz4, RSVD0, PM_TRIG1, RSVD2, RSVD3, 0xa050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio283_pz5, RSVD0, RSVD1, RSVD2, RSVD3, 0xa058, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio284_pz6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa060, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio285_pz7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa068, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio286_pal0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa070, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio287_pal1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa078, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio288_pal2, RSVD0, RSVD1, RSVD2, RSVD3, 0xa080, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(xhalt_trig_pz2, XHALT_TRIG, RSVD1, RSVD2, RSVD3, 0xa088, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio281_pz3, RSVD0, PM_TRIG0, RSVD2, RSVD3, 0xa090, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+};\n+\n+static const struct tegra_pingroup tegra264_aon_groups[] = {\n+\tPINGROUP(ao_retention_n_paa2, RSVD0, RSVD1, RSVD2, ISTCTRL_IST_DONE_N, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(batt_oc_paa3, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(power_on_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(vcomp_alert_paa1, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(bootv_ctl_n_paa4, RSVD0, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio00_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio07_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio08_pbb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio09_pbb1, RSVD0, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(hdmi_cec_paa6, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen2_i2c_scl_pcc0, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen2_i2c_sda_pcc1, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen3_i2c_scl_pcc2, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gen3_i2c_sda_pcc3, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(gp_pwm4_pcc4, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart0_tx_pcc5, UARTA_TXD, RSVD1, UARTL_TXD, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(uart0_rx_pcc6, UARTA_RXD, RSVD1, UARTL_RXD, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi2_sck_pcc7, SPI2_SCK, RSVD1, I2S9_SCLK, SOUNDWIRE0_CLK, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi2_miso_pdd0, SPI2_DIN, RSVD1, I2S9_SDATA_OUT, SOUNDWIRE0_DAT0, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi2_mosi_pdd1, SPI2_DOUT, RSVD1, I2S9_SDATA_IN, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(spi2_cs0_n_pdd2, SPI2_CS0, RSVD1, I2S9_LRCK, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio21_pdd3, RSVD0, TSC_SYNC1, DMIC5_DAT, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio22_pdd4, RSVD0, RSVD1, DMIC5_CLK, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio23_pdd5, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio24_pdd6, RSVD0, TSC_EDGE_OUT3, RSVD2, TSC_EDGE_OUT0D, 0x1070, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio25_pdd7, RSVD0, TSC_EDGE_OUT0, RSVD2, TSC_EDGE_OUT0A, 0x1078, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio26_pee0, RSVD0, TSC_EDGE_OUT1, RSVD2, TSC_EDGE_OUT0B, 0x1080, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio27_pee1, RSVD0, TSC_SYNC0, RSVD2, RSVD3, 0x1088, 0, Y, 5, 7, 6, 8, -1, 10, 11),\n+\tPINGROUP(soc_gpio28_pee2, L0L1_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1090, 0, N, -1, -1, -1, -1, -1, 10, -1),\n+\tPINGROUP(soc_gpio29_pee3, L2_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1098, 0, N, -1, -1, -1, -1, -1, 10, -1),\n+};\n+\n+static const struct tegra_pinctrl_soc_data tegra264_uphy_pinctrl = {\n+\t.pins = tegra264_uphy_pins,\n+\t.npins = ARRAY_SIZE(tegra264_uphy_pins),\n+\t.functions = tegra264_functions,\n+\t.nfunctions = ARRAY_SIZE(tegra264_functions),\n+\t.groups = tegra264_uphy_groups,\n+\t.ngroups = ARRAY_SIZE(tegra264_uphy_groups),\n+\t.hsm_in_mux = false,\n+\t.schmitt_in_mux = true,\n+\t.drvtype_in_mux = true,\n+\t.sfsel_in_mux = true,\n+};\n+\n+static const struct tegra_pinctrl_soc_data tegra264_main_pinctrl = {\n+\t.pins = tegra264_main_pins,\n+\t.npins = ARRAY_SIZE(tegra264_main_pins),\n+\t.functions = tegra264_functions,\n+\t.nfunctions = ARRAY_SIZE(tegra264_functions),\n+\t.groups = tegra264_main_groups,\n+\t.ngroups = ARRAY_SIZE(tegra264_main_groups),\n+\t.hsm_in_mux = false,\n+\t.schmitt_in_mux = true,\n+\t.drvtype_in_mux = true,\n+\t.sfsel_in_mux = true,\n+};\n+\n+static const struct tegra_pinctrl_soc_data tegra264_aon_pinctrl = {\n+\t.pins = tegra264_aon_pins,\n+\t.npins = ARRAY_SIZE(tegra264_aon_pins),\n+\t.functions = tegra264_functions,\n+\t.nfunctions = ARRAY_SIZE(tegra264_functions),\n+\t.groups = tegra264_aon_groups,\n+\t.ngroups = ARRAY_SIZE(tegra264_aon_groups),\n+\t.hsm_in_mux = false,\n+\t.schmitt_in_mux = true,\n+\t.drvtype_in_mux = true,\n+\t.sfsel_in_mux = true,\n+};\n+\n+static int tegra264_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tconst struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);\n+\n+\treturn tegra_pinctrl_probe(pdev, soc);\n+}\n+\n+static const struct of_device_id tegra264_pinctrl_of_match[] = {\n+\t{ .compatible = \"nvidia,tegra264-pinmux-uphy\", .data = &tegra264_uphy_pinctrl},\n+\t{ .compatible = \"nvidia,tegra264-pinmux-main\", .data = &tegra264_main_pinctrl},\n+\t{ .compatible = \"nvidia,tegra264-pinmux-aon\", .data = &tegra264_aon_pinctrl},\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, tegra264_pinctrl_of_match);\n+\n+static struct platform_driver tegra264_pinctrl_driver = {\n+\t.driver = {\n+\t\t.name = \"tegra264-pinctrl\",\n+\t\t.of_match_table = tegra264_pinctrl_of_match,\n+\t},\n+\t.probe = tegra264_pinctrl_probe,\n+};\n+\n+static int __init tegra264_pinctrl_init(void)\n+{\n+\treturn platform_driver_register(&tegra264_pinctrl_driver);\n+}\n+module_init(tegra264_pinctrl_init);\n+\n+static void __exit tegra264_pinctrl_exit(void)\n+{\n+\tplatform_driver_unregister(&tegra264_pinctrl_driver);\n+}\n+module_exit(tegra264_pinctrl_exit);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"NVIDIA Corporation\");\n+MODULE_DESCRIPTION(\"NVIDIA Tegra264 pinctrl driver\");\n","prefixes":["5/6"]}