{"id":2221415,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221415/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260408-hpe-gsc-upstream-v1-4-2be1fb7cbbfc@hpe.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260408-hpe-gsc-upstream-v1-4-2be1fb7cbbfc@hpe.com>","list_archive_url":null,"date":"2026-04-08T19:24:16","name":"[4/9] watchdog: Add HPE GSC watchdog driver","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"daddd64442996aa434cdcf86f0e460aed6298458","submitter":{"id":93099,"url":"http://patchwork.ozlabs.org/api/1.2/people/93099/?format=json","name":"Jorge Cisneros","email":"jorge.cisneros@hpe.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260408-hpe-gsc-upstream-v1-4-2be1fb7cbbfc@hpe.com/mbox/","series":[{"id":499288,"url":"http://patchwork.ozlabs.org/api/1.2/series/499288/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499288","date":"2026-04-08T19:24:17","name":"arm: hpe: Add HPE GSC (Gen12) BMC SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499288/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221415/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221415/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=hpe.com header.i=@hpe.com header.a=rsa-sha256\n header.s=pps0720 header.b=nSVqmSya;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=cc\n :content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pps0720; bh=Fa\n dC60KT/B5h2aPSJuhItBgpnUYaL6NRPb8xrgcRRh8=; b=nSVqmSya2A0Pnu4wyx\n FSPjEPuuXT1F34a9yVpsPBBsjMPs1EABXbiokpyowPDwZ5q2UK6c8AKweuunylHb\n DTQ9p1RLhicLGQnP33oPWk0fOCm2Afs16sOzJ6SH4Lh0pcgzK4crp4vW3zrEcpt+\n CX1vhLmR9pgvAicVsFMrQyCF3njWbweQ+tf28eyq3tKOeDFJ90QJNPmmjs5hKpZ5\n rFe++uGPjlO0Ocip4x/Nk6vrgOPiynp+s8yahBzSfgxtk6UUd8e7kf4u0zi5aEmQ\n YBqokpkwr4Czr3IU7D3zB34/aRXStIRt1gQyVy4S5cNDWvwDHsEj07hqLkI1VVkN\n ygqw==","From":"Jorge Cisneros ","Date":"Wed, 08 Apr 2026 19:24:16 +0000","Subject":"[PATCH 4/9] watchdog: Add HPE GSC watchdog driver","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260408-hpe-gsc-upstream-v1-4-2be1fb7cbbfc@hpe.com>","References":"<20260408-hpe-gsc-upstream-v1-0-2be1fb7cbbfc@hpe.com>","In-Reply-To":"<20260408-hpe-gsc-upstream-v1-0-2be1fb7cbbfc@hpe.com>","To":"u-boot@lists.denx.de","Cc":"Rayagonda Kokatanur ,\n Tom Rini , Jean-Marie Verdun ,\n Nick Hawkins ,\n Casey Connolly , Anshul Dalal ,\n Tien Fong Chee , Peng Fan ,\n Alif Zakuan Yuslaimi ,\n Tingting Meng , Alice Guo ,\n Quentin Schulz ,\n Ilias Apalodimas ,\n Tony Dinh ,\n Marek Vasut ,\n Stefan Roese ,\n Svyatoslav Ryhel ,\n Patrice Chotard ,\n Mattijs Korpershoek ,\n Shmuel Leib Melamud ,\n Lukasz Majewski ,\n Sumit Garg ,\n Chen-Yu Tsai , Justin Klaassen ,\n Neha Malcom Francis ,\n Jamie Gibbons ,\n Leo Yu-Chi Liang ,\n Jerome Forissier ,\n Simon Glass ,\n Neil Armstrong , Yao Zi ,\n Kuan-Wei Chiu ,\n \"Kory Maincent (TI.com)\" ,\n Raymond Mao ,\n Philip Molloy ,\n Jorge Cisneros ","X-Mailer":"b4 0.15.1","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDE4MSBTYWx0ZWRfX6HI9+/9pRAMS\n mtCO+wpgfdpANqGeT7hM7AkBTZlrF/svLpDC4DQ1m1BToGrRurbplkZX3uX9th0c88xHpxR7QYs\n MVdX1HDsM6za7XmXxtBJ83aCQPrskghpH67Lk09MVqACeZ8/rLh5jKZ6EAcovTb3DeDl3z4Vpwu\n VYRMrytF5dTTFViFpnivxhJDweUoMiCevFocej+kCyaxzj2XiM2O1mImTDaA+70ykN3EwgvSjCg\n oXanF/PBmkjVn5VNDXi4SqKsIQLS+LbpT/lBnRiPEg3MEHP85nwLOzD25YD7yMSrrMe1lEQVdaH\n xIp3X6/l7fy02JpF8qLtwCvJojl42IvJ2bryfCdhlhSBZwlGNx4Awd3lfhAwwSCSurqXpDWg2zP\n kgsiutxJIy0YH1m4r32HJYXOmZOW2B0RyjzyROGGZXq65H8pUoJXXY3GRa/5C2We31KRtibm1Qy\n KbjlUb+tkdvO3/0y3nQ==","X-Authority-Analysis":"v=2.4 cv=LJhWhpW9 c=1 sm=1 tr=0 ts=69d6ab66 cx=c_pps\n a=UObrlqRbTUrrdMEdGJ+KZA==:117 a=UObrlqRbTUrrdMEdGJ+KZA==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gQcMVamqm3wCPoSYhaRC:22 a=ModqzXLkJJ0tFyq98apW:22 a=MvuuwTCpAAAA:8\n a=NIagIq1R15lFhUNdsw8A:9 a=QEXdDO2ut3YA:10","X-Proofpoint-GUID":"GOkdmUhvl5-SIBKz1gmSGi8_W8FEy_ry","X-Proofpoint-ORIG-GUID":"GOkdmUhvl5-SIBKz1gmSGi8_W8FEy_ry","X-HPE-SCL":"-1","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_05,2026-04-08_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 clxscore=1015\n lowpriorityscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080181","X-Mailman-Approved-At":"Thu, 09 Apr 2026 15:00:51 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add watchdog driver for the HPE GSC SoC. The GSC watchdog uses two\nseparate register regions: a counter register and a control register.\nWriting the counter value resets the watchdog timer, while writing to\nthe control register enables or disables the watchdog.\n\nSupported operations: start, stop, reset, and expire_now.\n\nSigned-off-by: Jorge Cisneros \n---\n drivers/watchdog/Kconfig | 7 +++\n drivers/watchdog/Makefile | 1 +\n drivers/watchdog/gsc_wdt.c | 110 +++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 118 insertions(+)","diff":"diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig\nindex 35ae7d106b1..692a7eb4304 100644\n--- a/drivers/watchdog/Kconfig\n+++ b/drivers/watchdog/Kconfig\n@@ -195,6 +195,13 @@ config WDT_DAVINCI\n \t Select this to enable the watchdog timer for DaVinci SoCs such as the\n \t OMAP-L138.\n \n+config WDT_GSC\n+\tbool \"HPE GSC watchdog support\"\n+\tdepends on WDT\n+\thelp\n+\t Enable support for the watchdog timer in HPE GSC BMC SoC\n+\t used in HPE Gen12 servers.\n+\n config WDT_GPIO\n \tbool \"External gpio watchdog support\"\n \tdepends on WDT\ndiff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile\nindex 02e2674f8af..f7397e03527 100644\n--- a/drivers/watchdog/Makefile\n+++ b/drivers/watchdog/Makefile\n@@ -32,6 +32,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o\n obj-$(CONFIG_WDT_DA9063) += da9063-wdt.o\n obj-$(CONFIG_WDT_DAVINCI) += davinci_wdt.o\n obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o\n+obj-$(CONFIG_WDT_GSC) += gsc_wdt.o\n obj-$(CONFIG_$(SPL_TPL_)WDT_GPIO) += gpio_wdt.o\n obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o\n obj-$(CONFIG_WDT_MCF) += mcf_wdt.o\ndiff --git a/drivers/watchdog/gsc_wdt.c b/drivers/watchdog/gsc_wdt.c\nnew file mode 100644\nindex 00000000000..b535f47e052\n--- /dev/null\n+++ b/drivers/watchdog/gsc_wdt.c\n@@ -0,0 +1,110 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/* Copyright (C) 2022-2025 Hewlett Packard Enterprise Development LP */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#define MASK_WDGCS_ENABLE\tBIT(0)\n+#define MASK_WDGCS_RELOAD\tBIT(2)\n+#define MASK_WDGCS_NMIEN\tBIT(3)\n+#define MASK_WDGCS_WARN\t\tBIT(7)\n+\n+#define WDT_MAX_TIMEOUT_MS\t655350\n+#define SECS_TO_WDOG_TICKS(x)\t((x) * 100)\n+\n+struct gsc_wdt_priv {\n+\tvoid __iomem *counter;\n+\tvoid __iomem *control;\n+};\n+\n+static int gsc_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)\n+{\n+\tstruct gsc_wdt_priv *priv = dev_get_priv(dev);\n+\tu8 val;\n+\tu16 timeout_secs;\n+\n+\tif (timeout_ms > WDT_MAX_TIMEOUT_MS)\n+\t\ttimeout_ms = WDT_MAX_TIMEOUT_MS;\n+\telse if (timeout_ms == 0)\n+\t\ttimeout_ms = CONFIG_WATCHDOG_TIMEOUT_MSECS;\n+\n+\ttimeout_secs = timeout_ms / 1000;\n+\twritew(SECS_TO_WDOG_TICKS(timeout_secs), priv->counter);\n+\n+\tval = readb(priv->control);\n+\tval |= MASK_WDGCS_ENABLE;\n+\twriteb(val, priv->control);\n+\n+\treturn 0;\n+}\n+\n+static int gsc_wdt_stop(struct udevice *dev)\n+{\n+\tstruct gsc_wdt_priv *priv = dev_get_priv(dev);\n+\tu8 val;\n+\n+\tval = readb(priv->control);\n+\tval &= ~MASK_WDGCS_ENABLE;\n+\twriteb(val, priv->control);\n+\n+\treturn 0;\n+}\n+\n+static int gsc_wdt_reset(struct udevice *dev)\n+{\n+\tstruct gsc_wdt_priv *priv = dev_get_priv(dev);\n+\tu8 val;\n+\n+\tval = readb(priv->control);\n+\tval |= MASK_WDGCS_RELOAD;\n+\twriteb(val, priv->control);\n+\n+\treturn 0;\n+}\n+\n+static int gsc_wdt_expire_now(struct udevice *dev, ulong flags)\n+{\n+\treturn gsc_wdt_start(dev, 1, flags);\n+}\n+\n+static const struct wdt_ops gsc_wdt_ops = {\n+\t.start = gsc_wdt_start,\n+\t.reset = gsc_wdt_reset,\n+\t.stop = gsc_wdt_stop,\n+\t.expire_now = gsc_wdt_expire_now,\n+};\n+\n+static const struct udevice_id gsc_wdt_ids[] = {\n+\t{ .compatible = \"hpe,gsc-wdt\" },\n+\t{ }\n+};\n+\n+static int gsc_wdt_probe(struct udevice *dev)\n+{\n+\tstruct gsc_wdt_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->counter = dev_remap_addr_index(dev, 0);\n+\tif (!priv->counter)\n+\t\treturn -EINVAL;\n+\n+\tpriv->control = dev_remap_addr_index(dev, 1);\n+\tif (!priv->control)\n+\t\treturn -EINVAL;\n+\n+\tgsc_wdt_stop(dev);\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(gsc_wdt) = {\n+\t.name = \"gsc_wdt\",\n+\t.id = UCLASS_WDT,\n+\t.of_match = gsc_wdt_ids,\n+\t.probe = gsc_wdt_probe,\n+\t.priv_auto = sizeof(struct gsc_wdt_priv),\n+\t.ops = &gsc_wdt_ops,\n+};\n","prefixes":["4/9"]}