{"id":2221414,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221414/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260408-hpe-gsc-upstream-v1-2-2be1fb7cbbfc@hpe.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260408-hpe-gsc-upstream-v1-2-2be1fb7cbbfc@hpe.com>","list_archive_url":null,"date":"2026-04-08T19:24:14","name":"[2/9] arm: hpe: Add GSC SoC support","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"fce70fb8207b47191b7720f9dcbd3c42033bf32c","submitter":{"id":93099,"url":"http://patchwork.ozlabs.org/api/1.2/people/93099/?format=json","name":"Jorge Cisneros","email":"jorge.cisneros@hpe.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260408-hpe-gsc-upstream-v1-2-2be1fb7cbbfc@hpe.com/mbox/","series":[{"id":499288,"url":"http://patchwork.ozlabs.org/api/1.2/series/499288/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499288","date":"2026-04-08T19:24:17","name":"arm: hpe: Add HPE GSC (Gen12) BMC SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499288/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221414/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221414/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=hpe.com header.i=@hpe.com header.a=rsa-sha256\n header.s=pps0720 header.b=LLBAwvp+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=hpe.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n 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,\n Jamie Gibbons ,\n Leo Yu-Chi Liang ,\n Jerome Forissier ,\n Simon Glass ,\n Neil Armstrong , Yao Zi ,\n Kuan-Wei Chiu ,\n \"Kory Maincent (TI.com)\" ,\n Raymond Mao ,\n Philip Molloy ,\n Jorge Cisneros ","X-Mailer":"b4 0.15.1","X-Authority-Analysis":"v=2.4 cv=JPgLdcKb c=1 sm=1 tr=0 ts=69d6ab65 cx=c_pps\n a=FAnPgvRYq/vnBSvlTDCQOQ==:117 a=FAnPgvRYq/vnBSvlTDCQOQ==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gQcMVamqm3wCPoSYhaRC:22 a=ZSrvDirOKP4VPF05hnFf:22 a=MvuuwTCpAAAA:8\n a=nW4WiQT0LLkrqWE3KoYA:9 a=QEXdDO2ut3YA:10","X-Proofpoint-ORIG-GUID":"4bZIGNOHYYN1SKcD9UEnPh8sROkgyqOz","X-Proofpoint-GUID":"4bZIGNOHYYN1SKcD9UEnPh8sROkgyqOz","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDE4MSBTYWx0ZWRfX+H/EeXF59grn\n ksq6nrrXFqLOgmC+0b6TOOUSZaaaKz0mKYWSVSOPARIn2I1fSjVq+l7hLyvHZc4gP2dAq9zKMpB\n L2rH+v65RENFU8+b3vn+mKBMLOHu1CBFiRDe1S6AYVUFrh1Rcm2wk9W3U4V5PO98FLfJzrFd4qZ\n 9Zc3TlWt/OxFmj88leLG3KYCWuaTSuFRmGHpcEMuXg7N1JmCH+FjENAsj1o93OeBmgyXN2Q3wI5\n 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discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add core SoC support for the HPE GSC (Gen Server Controller), an ARM64\nBMC SoC used in HPE Gen12 ProLiant and Synergy servers.\n\nThis includes:\n- Kconfig entries for SOC_GSC with ARM64, I3C hub DT fixup, and VPD\n patching options (SYS_SOC set to \"gsc\")\n- SoC reset implementation via writel to GSC system control register\n- Architecture-level clock header for MACB Ethernet driver compatibility\n\nThe GSC reuses several GXP IP blocks (timer, SPI, I2C) while adding\nnew peripherals including a GICv3 interrupt controller, Cadence MACB\nGEM Ethernet, and a Denali DDR memory controller.\n\nSigned-off-by: Jorge Cisneros \n---\n arch/arm/include/asm/arch-gsc/clk.h | 14 ++++++++++++++\n arch/arm/mach-hpe/gsc/reset.c | 19 +++++++++++++++++++\n 2 files changed, 33 insertions(+)","diff":"diff --git a/arch/arm/include/asm/arch-gsc/clk.h b/arch/arm/include/asm/arch-gsc/clk.h\nnew file mode 100644\nindex 00000000000..19922c433d4\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-gsc/clk.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * HPE GSC SoC clock interface\n+ */\n+\n+#ifndef _ASM_ARCH_CLK_H_\n+#define _ASM_ARCH_CLK_H_\n+\n+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)\n+{\n+\treturn 50000000; /* 50 MHz */\n+}\n+\n+#endif /* _ASM_ARCH_CLK_H_ */\ndiff --git a/arch/arm/mach-hpe/gsc/reset.c b/arch/arm/mach-hpe/gsc/reset.c\nnew file mode 100644\nindex 00000000000..67fc83b2deb\n--- /dev/null\n+++ b/arch/arm/mach-hpe/gsc/reset.c\n@@ -0,0 +1,19 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * GSC SoC reset\n+ *\n+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.\n+ * Author: Gilbert Chen \n+ */\n+\n+#include \n+\n+#define GSC_CCR\t0xC0000000\n+\n+void reset_cpu(void)\n+{\n+\twritel(1, GSC_CCR);\n+\n+\twhile (1)\n+\t\t;\t/* loop forever till reset */\n+}\n","prefixes":["2/9"]}