{"id":2221372,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2221372/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260409102501.1447628-1-poros@redhat.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.2/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260409102501.1447628-1-poros@redhat.com>","list_archive_url":null,"date":"2026-04-09T10:25:01","name":"[iwl-net,v5] ice: fix missing dpll notifications for SW pins","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e8908d2e418199620a7fd541307f0c0e19c29f23","submitter":{"id":74657,"url":"http://patchwork.ozlabs.org/api/1.2/people/74657/?format=json","name":"Petr Oros","email":"poros@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260409102501.1447628-1-poros@redhat.com/mbox/","series":[{"id":499268,"url":"http://patchwork.ozlabs.org/api/1.2/series/499268/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499268","date":"2026-04-09T10:25:01","name":"[iwl-net,v5] ice: fix missing dpll notifications for SW pins","version":5,"mbox":"http://patchwork.ozlabs.org/series/499268/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221372/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221372/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=ecudjgi9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.138; 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client-ip=170.10.129.124;\n helo=us-smtp-delivery-124.mimecast.com; envelope-from=poros@redhat.com;\n receiver=","DMARC-Filter":"OpenDMARC Filter v1.4.2 smtp4.osuosl.org 7E1974072C","X-MC-Unique":"EiTJoYSSOxeutNoL5oRKKA-1","X-Mimecast-MFC-AGG-ID":"EiTJoYSSOxeutNoL5oRKKA_1775730310","From":"Petr Oros ","To":"netdev@vger.kernel.org","Date":"Thu, 9 Apr 2026 12:25:01 +0200","Message-ID":"<20260409102501.1447628-1-poros@redhat.com>","MIME-Version":"1.0","X-Scanned-By":"MIMEDefang 3.4.1 on 10.30.177.93","X-Mimecast-MFC-PROC-ID":"L5EQCHrmogvoJAzMiSn-hdZ9rIvOaO9xMT4vqAxXtME_1775730310","X-Mimecast-Originator":"redhat.com","Content-Transfer-Encoding":"8bit","content-type":"text/plain; charset=\"US-ASCII\"; x-default=true","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=redhat.com;\n s=mimecast20190719; t=1775730317;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding;\n bh=7yDIKdr9fH0AJA/LkGSLtUe86dHZlLjk/Pi0ptBjyB0=;\n b=Hh6SBfqeOAToQxR36FiV388pq1empnXQ03oG2tdIeXnGB2+JkKETaJ829gi4URFjhisSwS\n sDHjntXWIZMn417G8qm6KgNKQ+nVToQC2I5HUhv8KcASPsGpkWcel5eLQT4FXiOYJj7936\n Xvp9VsXjv5gTZmAPEqX1ElNj548nGmU=","X-Mailman-Original-Authentication-Results":["smtp4.osuosl.org;\n dmarc=pass (p=quarantine dis=none)\n header.from=redhat.com","smtp4.osuosl.org;\n dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com\n header.a=rsa-sha256 header.s=mimecast20190719 header.b=Hh6SBfqe"],"Subject":"[Intel-wired-lan] [PATCH iwl-net v5] ice: fix missing dpll\n notifications for SW pins","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"Przemek Kitszel ,\n Eric Dumazet ,\n Arkadiusz Kubalewski ,\n Andrew Lunn ,\n Tony Nguyen ,\n Simon Horman , intel-wired-lan@lists.osuosl.org,\n Jakub Kicinski , Paolo Abeni ,\n \"David S. Miller\" , linux-kernel@vger.kernel.org","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"The SMA/U.FL pin redesign (commit 2dd5d03c77e2 (\"ice: redesign dpll\nsma/u.fl pins control\")) introduced software-controlled pins that wrap\nbacking CGU input/output pins, but never updated the notification and\ndata paths to propagate pin events to these SW wrappers.\n\nThe periodic work sends dpll_pin_change_ntf() only for direct CGU input\npins. SW pins that wrap these inputs never receive change or phase\noffset notifications, so userspace consumers such as synce4l monitoring\nSMA pins via dpll netlink never learn about state transitions or phase\noffset updates. Similarly, ice_dpll_phase_offset_get() reads the SW\npin's own phase_offset field which is never updated; the PPS monitor\nwrites to the backing CGU input's field instead.\n\nOn top of that, when SMA or U.FL pin state changes via PCA9575 GPIO\nwrite, the paired pin's state also changes because they share physical\nsignal paths, but no notification is sent for the peer pin.\n\nFix by introducing ice_dpll_pin_ntf(), a wrapper around\ndpll_pin_change_ntf() that also notifies any registered SMA/U.FL pin\nwhose backing CGU input matches. Replace all direct\ndpll_pin_change_ntf() calls in the periodic notification paths with\nthis wrapper. Fix ice_dpll_phase_offset_get() to return the backing\nCGU input's phase_offset for input-direction SW pins. Add\nice_dpll_sw_pin_notify_peer() to send a notification for the paired\nSW pin after PCA9575 writes in ice_dpll_sma_direction_set() and\nice_dpll_ufl_pin_state_set().\n\nFixes: 2dd5d03c77e2 (\"ice: redesign dpll sma/u.fl pins control\")\nSigned-off-by: Petr Oros \n---\nv5:\n - add ice_dpll_sw_pin_notify_peer() for SMA/U.FL peer notification\n when PCA9575 routing changes affect the paired pin (reported by\n Intel test: SMA state change did not log U.FL status change in\n subscribe monitor)\nv4: https://lore.kernel.org/all/20260319205256.998876-1-poros@redhat.com/\nv3: https://lore.kernel.org/all/20260220140700.2910174-1-poros@redhat.com/\nv2: https://lore.kernel.org/all/20260219131500.2271897-1-poros@redhat.com/\nv1: https://lore.kernel.org/all/20260218211414.1411163-1-poros@redhat.com/\n---\n drivers/net/ethernet/intel/ice/ice_dpll.c | 74 +++++++++++++++++++----\n 1 file changed, 63 insertions(+), 11 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c\nindex 3f8cd5b8298b57..d817f17dcf1951 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dpll.c\n+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c\n@@ -1154,6 +1154,30 @@ ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv,\n \t\t\t\t extack, ICE_DPLL_PIN_TYPE_INPUT);\n }\n \n+/**\n+ * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change\n+ * @d: pointer to dplls struct\n+ * @changed: the SW pin that was explicitly changed (already notified by dpll core)\n+ *\n+ * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and\n+ * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO\n+ * expander, the paired pin's state may also change. Send a change\n+ * notification for the peer pin so userspace consumers monitoring the\n+ * peer via dpll netlink learn about the update.\n+ *\n+ * Context: Can be called under pf->dplls.lock, dpll_pin_change_ntf() is safe.\n+ */\n+static void ice_dpll_sw_pin_notify_peer(struct ice_dplls *d,\n+\t\t\t\t\tstruct ice_dpll_pin *changed)\n+{\n+\tstruct ice_dpll_pin *peer;\n+\n+\tpeer = (changed >= d->sma && changed < d->sma + ICE_DPLL_PIN_SW_NUM) ?\n+\t\t&d->ufl[changed->idx] : &d->sma[changed->idx];\n+\tif (peer->pin)\n+\t\tdpll_pin_change_ntf(peer->pin);\n+}\n+\n /**\n * ice_dpll_sma_direction_set - set direction of SMA pin\n * @p: pointer to a pin\n@@ -1233,6 +1257,8 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p,\n \t\t\tret = ice_dpll_pin_state_update(p->pf, target,\n \t\t\t\t\t\t\ttype, extack);\n \t}\n+\tif (!ret)\n+\t\tice_dpll_sw_pin_notify_peer(d, p);\n \n \treturn ret;\n }\n@@ -1334,6 +1360,7 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv,\n \t\t\t\t\textack);\n \tif (ret)\n \t\tgoto unlock;\n+\tice_dpll_sw_pin_notify_peer(&pf->dplls, p);\n \n \tif (enable)\n \t\tret = ice_dpll_pin_enable(hw, target, d->dpll_idx, type, extack);\n@@ -1963,7 +1990,10 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,\n \t\t\t\t d->active_input == p->input->pin))\n \t\t*phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;\n \telse if (d->phase_offset_monitor_period)\n-\t\t*phase_offset = p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;\n+\t\t*phase_offset = (p->input &&\n+\t\t\t\t p->direction == DPLL_PIN_DIRECTION_INPUT ?\n+\t\t\t\t p->input->phase_offset :\n+\t\t\t\t p->phase_offset) * ICE_DPLL_PHASE_OFFSET_FACTOR;\n \telse\n \t\t*phase_offset = 0;\n \tmutex_unlock(&pf->dplls.lock);\n@@ -2657,6 +2687,27 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)\n \treturn pci_get_dsn(pf->pdev);\n }\n \n+/**\n+ * ice_dpll_pin_ntf - notify pin change including any SW pin wrappers\n+ * @dplls: pointer to dplls struct\n+ * @pin: the dpll_pin that changed\n+ *\n+ * Send a change notification for @pin and for any registered SMA/U.FL pin\n+ * whose backing CGU input matches @pin.\n+ */\n+static void ice_dpll_pin_ntf(struct ice_dplls *dplls, struct dpll_pin *pin)\n+{\n+\tdpll_pin_change_ntf(pin);\n+\tfor (int i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) {\n+\t\tif (dplls->sma[i].pin && dplls->sma[i].input &&\n+\t\t dplls->sma[i].input->pin == pin)\n+\t\t\tdpll_pin_change_ntf(dplls->sma[i].pin);\n+\t\tif (dplls->ufl[i].pin && dplls->ufl[i].input &&\n+\t\t dplls->ufl[i].input->pin == pin)\n+\t\t\tdpll_pin_change_ntf(dplls->ufl[i].pin);\n+\t}\n+}\n+\n /**\n * ice_dpll_notify_changes - notify dpll subsystem about changes\n * @d: pointer do dpll\n@@ -2665,6 +2716,7 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)\n */\n static void ice_dpll_notify_changes(struct ice_dpll *d)\n {\n+\tstruct ice_dplls *dplls = &d->pf->dplls;\n \tbool pin_notified = false;\n \n \tif (d->prev_dpll_state != d->dpll_state) {\n@@ -2673,17 +2725,17 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)\n \t}\n \tif (d->prev_input != d->active_input) {\n \t\tif (d->prev_input)\n-\t\t\tdpll_pin_change_ntf(d->prev_input);\n+\t\t\tice_dpll_pin_ntf(dplls, d->prev_input);\n \t\td->prev_input = d->active_input;\n \t\tif (d->active_input) {\n-\t\t\tdpll_pin_change_ntf(d->active_input);\n+\t\t\tice_dpll_pin_ntf(dplls, d->active_input);\n \t\t\tpin_notified = true;\n \t\t}\n \t}\n \tif (d->prev_phase_offset != d->phase_offset) {\n \t\td->prev_phase_offset = d->phase_offset;\n \t\tif (!pin_notified && d->active_input)\n-\t\t\tdpll_pin_change_ntf(d->active_input);\n+\t\t\tice_dpll_pin_ntf(dplls, d->active_input);\n \t}\n }\n \n@@ -2712,6 +2764,7 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf)\n \n /**\n * ice_dpll_pins_notify_mask - notify dpll subsystem about bulk pin changes\n+ * @dplls: pointer to dplls struct\n * @pins: array of ice_dpll_pin pointers registered within dpll subsystem\n * @pin_num: number of pins\n * @phase_offset_ntf_mask: bitmask of pin indexes to notify\n@@ -2721,15 +2774,14 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf)\n *\n * Context: Must be called while pf->dplls.lock is released.\n */\n-static void ice_dpll_pins_notify_mask(struct ice_dpll_pin *pins,\n+static void ice_dpll_pins_notify_mask(struct ice_dplls *dplls,\n+\t\t\t\t struct ice_dpll_pin *pins,\n \t\t\t\t u8 pin_num,\n \t\t\t\t u32 phase_offset_ntf_mask)\n {\n-\tint i = 0;\n-\n-\tfor (i = 0; i < pin_num; i++)\n-\t\tif (phase_offset_ntf_mask & (1 << i))\n-\t\t\tdpll_pin_change_ntf(pins[i].pin);\n+\tfor (int i = 0; i < pin_num; i++)\n+\t\tif (phase_offset_ntf_mask & BIT(i))\n+\t\t\tice_dpll_pin_ntf(dplls, pins[i].pin);\n }\n \n /**\n@@ -2905,7 +2957,7 @@ static void ice_dpll_periodic_work(struct kthread_work *work)\n \tice_dpll_notify_changes(de);\n \tice_dpll_notify_changes(dp);\n \tif (phase_offset_ntf)\n-\t\tice_dpll_pins_notify_mask(d->inputs, d->num_inputs,\n+\t\tice_dpll_pins_notify_mask(d, d->inputs, d->num_inputs,\n \t\t\t\t\t phase_offset_ntf);\n \n resched:\n","prefixes":["iwl-net","v5"]}