{"id":2220935,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2220935/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-8-aswin.murugan@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260408121841.186410-8-aswin.murugan@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-08T12:18:41","name":"[v4,7/7] misc: update API documentation for bit field support in NVMEM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ab8f638a961705c9c16dcda04b825327ddf95452","submitter":{"id":90811,"url":"http://patchwork.ozlabs.org/api/1.2/people/90811/?format=json","name":"Aswin Murugan","email":"aswin.murugan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.2/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-8-aswin.murugan@oss.qualcomm.com/mbox/","series":[{"id":499133,"url":"http://patchwork.ozlabs.org/api/1.2/series/499133/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499133","date":"2026-04-08T12:18:34","name":"qcom: Add NVMEM bitfield support and reboot���mode integration","version":4,"mbox":"http://patchwork.ozlabs.org/series/499133/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220935/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220935/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=K0VYV84z;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=JEx6ocKN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"K0VYV84z\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"JEx6ocKN\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frMcX6Jgyz1xy1\n\tfor ; Wed, 08 Apr 2026 22:21:32 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 41D148418C;\n\tWed, 8 Apr 2026 14:21:27 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id 026308414B; Wed, 8 Apr 2026 14:21:26 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3A6FC841C2\n for ; Wed, 8 Apr 2026 14:21:21 +0200 (CEST)","from pps.filterd (m0279870.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6387Q4CK2451202\n for ; Wed, 8 Apr 2026 12:21:19 GMT","from mail-pg1-f197.google.com (mail-pg1-f197.google.com\n [209.85.215.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddae6aq0s-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Wed, 08 Apr 2026 12:21:19 +0000 (GMT)","by mail-pg1-f197.google.com with SMTP id\n 41be03b00d2f7-b630b4d8d52so3950708a12.3\n for ; Wed, 08 Apr 2026 05:21:19 -0700 (PDT)","from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, gchan9527@gmail.com, ilias.apalodimas@linaro.org,\n mkorpershoek@kernel.org, marek.vasut+renesas@mailbox.org,\n hs@nabladev.com, msp@baylibre.com, ravi@prevas.dk,\n dinesh.maniyam@altera.com, sajattack@postmarketos.org,\n peng.fan@nxp.com, quentin.schulz@cherry.de,\n jamie.gibbons@microchip.com, mateuslima.ti@gmail.com,\n justin@tidylabs.net, wens@kernel.org, n-francis@ti.com,\n ycliang@andestech.com, jerome.forissier@arm.com, clamor95@gmail.com,\n u-boot@lists.denx.de, u-boot-qcom@groups.io","Subject":"[PATCH v4 7/7] misc: update API documentation for bit field support\n in NVMEM","Date":"Wed, 8 Apr 2026 17:48:41 +0530","Message-Id":"<20260408121841.186410-8-aswin.murugan@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>","References":"<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDExMiBTYWx0ZWRfX6Vmqmfu4PGzH\n lOXASTkOO2M8daCm7ypSNCI6sRcEVIMFLF+35GOXY0z6NWR5fqc3WF+Pb1CdLz6qaYInCguNuKl\n cT37dcbGOeEBenX8AKEaGizsvsvlWpNK46DDdMZCKYdfyws+RxBFueNNOunO/ZEgLGQkqKa5+D+\n OMU3tDImY87DxdY6iDYsoWcMWQymTh7GfwAw7qo4MwnJPoWKTX8oGNiMm4jYcKGqZCJeJ9+Kd5y\n ZvfsMOAlT23bq+2cRPeNRJnV1Su4Rfvx/7Yy3OIstvzGf8tuZqcj7Heqw9Qk9UGSXsWRMy4C6sC\n svPrjOkZ623bOW3rom1Ak7rR2n1vYOmnY+oOR2awQKww5GaOEhUsDoTZzT7qUUtxK5LVAExFjBl\n 5DzHEpCAzkfKjwk3Y352D4/G4cv9FiHb3pXvdnio4UknjlxJekJyJyutU+Ghz60mzwMalpxFKJa\n EUbPGzZ5FJcGckSe5Jg==","X-Proofpoint-GUID":"8qtxsLyAPx5zluVTVIdcsOsVa_5ewHfc","X-Proofpoint-ORIG-GUID":"8qtxsLyAPx5zluVTVIdcsOsVa_5ewHfc","X-Authority-Analysis":"v=2.4 cv=K4AS2SWI c=1 sm=1 tr=0 ts=69d6483f cx=c_pps\n a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8\n a=xnw-sE8SsPs_kYMhUbAA:9 a=bFCP_H2QrGi7Okbo017w:22","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015\n phishscore=0 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000\n definitions=main-2604080112","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Update the nvmem_cell_read() and nvmem_cell_write() documentation to\ndescribe the new bit field operation mode.\n\nThe documentation now clearly explains:\n\nFor bit field mode (nbits > 0):\n- Read: extracts the bit field from raw hardware bytes\n- Write: performs read-modify-write to preserve other bits\n- Requirements: buffer size must be sizeof(u32), cell size <= 4 bytes\n\nFor non-bit-field mode (nbits == 0):\n- Read/Write: direct byte-level access\n- Requirements: buffer size must equal the cell size\n\nThis helps developers understand when to use each mode and the\nassociated buffer size requirements.\n\nSigned-off-by: Aswin Murugan \n---\nChanges in v4:\n1. Added explicit documentation for all `@cell` parameters:\n - `@cell->offset` - Byte offset within NVMEM device\n - `@cell->size` - Size of cell in bytes\n - `@cell->nbits` - Number of bits (0 = byte-level mode)\n - `@cell->bit_offset` - Starting bit position\n---\n include/nvmem.h | 36 ++++++++++++++++++++++++++++++++----\n 1 file changed, 32 insertions(+), 4 deletions(-)","diff":"diff --git a/include/nvmem.h b/include/nvmem.h\nindex dd82122f16f..c3d845c3a7e 100644\n--- a/include/nvmem.h\n+++ b/include/nvmem.h\n@@ -43,13 +43,27 @@ struct udevice;\n \n /**\n * nvmem_cell_read() - Read the value of an nvmem cell\n- * @cell: The nvmem cell to read\n+ * @cell: The nvmem cell to read, containing:\n+ * - @cell->offset: Byte offset within the NVMEM device\n+ * - @cell->size: Size of the cell in bytes\n+ * - @cell->nbits: Number of bits to extract (0 = read entire cell)\n+ * - @cell->bit_offset: Starting bit position for extraction\n * @buf: The buffer to read into\n * @size: The size of @buf\n *\n+ * For cells with bit fields (@cell->nbits > 0), this function:\n+ * - Reads the raw bytes from @cell->offset in hardware\n+ * - Extracts the bit field using @cell->bit_offset and @cell->nbits\n+ * - Returns the extracted value in @buf\n+ * - Requires @size == sizeof(u32) and @cell->size <= sizeof(u32)\n+ *\n+ * For cells without bit fields (@cell->nbits == 0):\n+ * - Reads raw bytes directly from @cell->offset\n+ * - Requires @size == @cell->size\n+ *\n * Return:\n * * 0 on success\n- * * -EINVAL if @buf is not the same size as @cell.\n+ * * -EINVAL if @size doesn't match requirements\n * * -ENOSYS if CONFIG_NVMEM is disabled\n * * A negative error if there was a problem reading the underlying storage\n */\n@@ -57,13 +71,27 @@ int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size);\n \n /**\n * nvmem_cell_write() - Write a value to an nvmem cell\n- * @cell: The nvmem cell to write\n+ * @cell: The nvmem cell to write, containing:\n+ * - @cell->offset: Byte offset within the NVMEM device\n+ * - @cell->size: Size of the cell in bytes\n+ * - @cell->nbits: Number of bits to write (0 = write entire cell)\n+ * - @cell->bit_offset: Starting bit position for insertion\n * @buf: The buffer to write from\n * @size: The size of @buf\n *\n+ * For cells with bit fields (@cell->nbits > 0), this function:\n+ * - Performs Read-Modify-Write to preserve other bits at @cell->offset\n+ * - Masks and shifts the value to @cell->bit_offset position\n+ * - Merges with existing bits outside the @cell->nbits field\n+ * - Requires @size == sizeof(u32) and @cell->size <= sizeof(u32)\n+ *\n+ * For cells without bit fields (@cell->nbits == 0):\n+ * - Writes raw bytes directly to @cell->offset\n+ * - Requires @size == @cell->size\n+ *\n * Return:\n * * 0 on success\n- * * -EINVAL if @buf is not the same size as @cell\n+ * * -EINVAL if @size doesn't match requirements\n * * -ENOSYS if @cell is read-only, or if CONFIG_NVMEM is disabled\n * * A negative error if there was a problem writing the underlying storage\n */\n","prefixes":["v4","7/7"]}