{"id":2220932,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2220932/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-5-aswin.murugan@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260408121841.186410-5-aswin.murugan@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-08T12:18:38","name":"[v4,4/7] dts: qcs615-ride-u-boot.dtsi: Add reboot-mode support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"12e3a3d22afb3e8c8a1fb8f05fef9ea67961b8d6","submitter":{"id":90811,"url":"http://patchwork.ozlabs.org/api/1.2/people/90811/?format=json","name":"Aswin Murugan","email":"aswin.murugan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.2/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-5-aswin.murugan@oss.qualcomm.com/mbox/","series":[{"id":499133,"url":"http://patchwork.ozlabs.org/api/1.2/series/499133/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499133","date":"2026-04-08T12:18:34","name":"qcom: Add NVMEM bitfield support and reboot���mode integration","version":4,"mbox":"http://patchwork.ozlabs.org/series/499133/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220932/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220932/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=XvUAVnUf;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=E+COyjfM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"XvUAVnUf\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"E+COyjfM\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frMc01zJfz1xy1\n\tfor ; Wed, 08 Apr 2026 22:21:04 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 8625984118;\n\tWed, 8 Apr 2026 14:20:59 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id EB97984150; Wed, 8 Apr 2026 14:20:57 +0200 (CEST)","from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 631A18416F\n for ; Wed, 8 Apr 2026 14:20:55 +0200 (CEST)","from pps.filterd (m0279862.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6388ERsQ1796841\n for ; Wed, 8 Apr 2026 12:20:53 GMT","from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dd51dc3v8-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Wed, 08 Apr 2026 12:20:53 +0000 (GMT)","by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-82c7a84a43eso9528204b3a.0\n for ; Wed, 08 Apr 2026 05:20:53 -0700 (PDT)","from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, gchan9527@gmail.com, ilias.apalodimas@linaro.org,\n mkorpershoek@kernel.org, marek.vasut+renesas@mailbox.org,\n hs@nabladev.com, msp@baylibre.com, ravi@prevas.dk,\n dinesh.maniyam@altera.com, sajattack@postmarketos.org,\n peng.fan@nxp.com, quentin.schulz@cherry.de,\n jamie.gibbons@microchip.com, mateuslima.ti@gmail.com,\n justin@tidylabs.net, wens@kernel.org, n-francis@ti.com,\n ycliang@andestech.com, jerome.forissier@arm.com, clamor95@gmail.com,\n u-boot@lists.denx.de, u-boot-qcom@groups.io","Subject":"[PATCH v4 4/7] dts: qcs615-ride-u-boot.dtsi: Add reboot-mode support","Date":"Wed, 8 Apr 2026 17:48:38 +0530","Message-Id":"<20260408121841.186410-5-aswin.murugan@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>","References":"<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"kRKj5O0pWNyzj34FCtYtyUuexZnSdc9s","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDExMiBTYWx0ZWRfXzukG49Qa9N2v\n rg92K7XqFuxbMo12d7HePDybE/jNBenTSS+41gBH8tImn5CPSVDraO4C1k8ahincGbRKmqBkx63\n n/J3oqPKwmDD+41Q6TFVPzHV2YhmvzQN7tfF2o/Vuo3id0F52b33toofBMM9vJ3V2/3oLwlst0B\n t4C50RELrrJYYVtGMEk5IkvejLf/OJqKbZv633nAyjPMikxpSefN/MOtcGRyrDQF8/C1X/s/+JL\n OdWtOPHuD34ZFywx9aWyf78cJYErc8bc5yNGY0ej/nZfOWS+ZLNGGHoGyMtU1Dar2sMXuxPYCxh\n e6sbTklka40MSf7maDzrBBORhrn+b9tFphAtOAW6ey3B3jHU1PAmbSqPhsgBnQ/xI1JXfx+Tldd\n I8vYEnQ0vJ4Npzs9MNFd9bMydqYTJPreSCXLQpmsRBohbaG+aGepOVRhRk4PdPF3j67lK9DXriT\n n8fQRGY275v0bfDUWmw==","X-Authority-Analysis":"v=2.4 cv=AcaB2XXG c=1 sm=1 tr=0 ts=69d64825 cx=c_pps\n a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8\n a=yUmxN5dSmvX78ioYZS4A:9 a=OpyuDcXvxspvyRM73sMx:22","X-Proofpoint-GUID":"kRKj5O0pWNyzj34FCtYtyUuexZnSdc9s","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0\n phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080112","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"The PM8150 PMIC on this platform uses the older PON (Power On) register\narchitecture rather than dedicated SDAM regions found in newer PMIC\ngenerations. To enable reboot-mode functionality with the unified\nNVMEM-based approach, add a compatibility wrapper that exposes PON\nregisters through the SDAM NVMEM interface.\n\nAdd device tree configuration:\n- NVMEM node with compatible \"qcom,spmi-sdam\" wrapping PON registers\n- Uses 'ranges' property to map the PON register block at offset 0x800\n- NVMEM cell at offset 0x8F (PON_SOFT_RB_SPARE register)\n- 7-bit field (bits [7:1]) for reboot reason, preserving bit 0\n- Mode mappings: bootloader=0x02, recovery=0x01\n\nThis wrapper allows the SDAM NVMEM driver to access PON registers\ntransparently, providing a unified interface for both PON-based (older)\nand SDAM-based (newer) PMIC generations.\n\nThe PON_SOFT_RB_SPARE register persists across warm resets and is\nautomatically cleared on power cycle.\n\nSigned-off-by: Aswin Murugan \n---\nChanges in v4:\n1. Changed bits property as 'bits = <1 7>'\n\nChanges in v3:\n1. No change in v3\n---\n arch/arm/dts/qcs615-ride-u-boot.dtsi | 26 ++++++++++++++++++++++++++\n 1 file changed, 26 insertions(+)","diff":"diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi\nindex 68fffc70fcb..687e9a67a9f 100644\n--- a/arch/arm/dts/qcs615-ride-u-boot.dtsi\n+++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi\n@@ -11,4 +11,30 @@\n \t\t <0x0 0xc0000000 0x0 0xc0000000>,\n \t\t <0x1 0x80000000 0x1 0x00000000>;\n \t};\n+\n+\treboot-mode {\n+\t\tcompatible = \"nvmem-reboot-mode\";\n+\t\tnvmem-cells = <&reboot_reason>;\n+\t\tnvmem-cell-names = \"reboot-mode\";\n+\n+\t\tmode-bootloader = <0x02>;\n+\t\tmode-recovery = <0x01>;\n+\t};\n+};\n+\n+&pm8150_0 {\n+\t/* Virtual NVMEM node for PON-based reboot reason storage */\n+\tnvram@800 {\n+\t\tcompatible = \"qcom,spmi-sdam\";\n+\t\treg = <0x800>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0x00 0x800 0x100>;\n+\n+\t\t/* Reboot reason cell at PON_SOFT_RB_SPARE (0x88F) */\n+\t\treboot_reason: reboot-reason@8f {\n+\t\t\treg = <0x8f 0x1>;\n+\t\t\tbits = <1 7>;\n+\t\t};\n+\t};\n };\n","prefixes":["v4","4/7"]}