{"id":2220738,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2220738/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260407223447.4956-4-andre.przywara@arm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260407223447.4956-4-andre.przywara@arm.com>","list_archive_url":null,"date":"2026-04-07T22:34:47","name":"[3/3] sunxi: configs: enable power LEDs on 64-bit boards","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2362f531d2b6f27bfb3c74f6d13dd0ddd0f8bc0d","submitter":{"id":61837,"url":"http://patchwork.ozlabs.org/api/1.2/people/61837/?format=json","name":"Andre Przywara","email":"andre.przywara@arm.com"},"delegate":{"id":114289,"url":"http://patchwork.ozlabs.org/api/1.2/users/114289/?format=json","username":"apritzel","first_name":"Andre","last_name":"Przywara","email":"andre.przywara@arm.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260407223447.4956-4-andre.przywara@arm.com/mbox/","series":[{"id":499043,"url":"http://patchwork.ozlabs.org/api/1.2/series/499043/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499043","date":"2026-04-07T22:34:45","name":"sunxi: Fix and extend SPL power LED support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499043/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220738/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220738/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=foss header.b=MEnmCy3J;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Wed, 8 Apr 2026 00:35:06 +0200 (CEST)","from foss.arm.com (foss.arm.com [217.140.110.172])\n by phobos.denx.de (Postfix) with ESMTP id 92FF084118\n for ; Wed, 8 Apr 2026 00:35:03 +0200 (CEST)","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F5E339E7;\n Tue, 7 Apr 2026 15:34:57 -0700 (PDT)","from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n EFFC83F632; Tue, 7 Apr 2026 15:35:01 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss;\n t=1775601303; bh=6iSubdnYP9CJiM8NfOJBSq3KCcye7gvbMT4QpGfrlC4=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=MEnmCy3Jp1J09PTUMrAEhjLCZao4in+vBqi5WuSOgLR8f7fKJHBpgfqsEy5PXP/Pm\n VLXY578ajxy9oH+0CZy9pKIO2XUA8o9v/sC1iXt4GRChzWTyRcqJNGxQNb6DNQ5qWQ\n CTvEJCxOMU+OWfA1wyHvIRNOURsmqvX0AKNnCeTE=","From":"Andre Przywara ","To":"u-boot@lists.denx.de","Cc":"Tom Rini , Quentin Schulz ,\n Jernej Skrabec ,\n Paul Kocialkowski , linux-sunxi@lists.linux.dev","Subject":"[PATCH 3/3] sunxi: configs: enable power LEDs on 64-bit boards","Date":"Wed, 8 Apr 2026 00:34:47 +0200","Message-ID":"<20260407223447.4956-4-andre.przywara@arm.com>","X-Mailer":"git-send-email 2.46.4","In-Reply-To":"<20260407223447.4956-1-andre.przywara@arm.com>","References":"<20260407223447.4956-1-andre.przywara@arm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"We recently gained a simple way to enable a power LED very early in the\nSPL boot, through simple Kconfig variables.\n\nAdd those symbols to those boards' defconfigs where the DT indicates a\ndefault-on power LED. The number used is * 32 + ,\nan active low setup means CONFIG_SPL_SUNXI_LED_STATUS_STATE must be\nundefined.\n\nThis will light up the power LED very early in the (SPL) boot phase on\nthose 64-bit boards.\n\nSigned-off-by: Andre Przywara \n---\n configs/anbernic_rg35xx_h700_defconfig | 3 +++\n configs/bananapi_m64_defconfig | 3 +++\n configs/beelink_gs1_defconfig | 3 +++\n configs/liontron-h-a133l_defconfig | 3 +++\n configs/nanopi_neo2_defconfig | 3 +++\n configs/nanopi_neo_plus2_defconfig | 3 +++\n configs/orangepi_3_defconfig | 3 +++\n configs/orangepi_lite2_defconfig | 3 +++\n configs/orangepi_pc2_defconfig | 3 +++\n configs/orangepi_prime_defconfig | 3 +++\n configs/orangepi_zero2_defconfig | 3 +++\n configs/orangepi_zero_plus2_defconfig | 3 +++\n configs/orangepi_zero_plus_defconfig | 3 +++\n configs/radxa-cubie-a5e_defconfig | 3 +++\n configs/tanix_tx1_defconfig | 3 +++\n 15 files changed, 45 insertions(+)","diff":"diff --git a/configs/anbernic_rg35xx_h700_defconfig b/configs/anbernic_rg35xx_h700_defconfig\nindex 2fa57cbecce..fb3df175521 100644\n--- a/configs/anbernic_rg35xx_h700_defconfig\n+++ b/configs/anbernic_rg35xx_h700_defconfig\n@@ -16,6 +16,9 @@ CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1=y\n CONFIG_MACH_SUN50I_H616=y\n CONFIG_SUNXI_DRAM_H616_LPDDR4=y\n CONFIG_R_I2C_ENABLE=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=268\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n CONFIG_SPL_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_MVTWSI=y\ndiff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig\nindex d957071cb13..413de4919d5 100644\n--- a/configs/bananapi_m64_defconfig\n+++ b/configs/bananapi_m64_defconfig\n@@ -4,6 +4,9 @@ CONFIG_DEFAULT_DEVICE_TREE=\"sun50i-a64-bananapi-m64\"\n CONFIG_SPL=y\n CONFIG_MACH_SUN50I=y\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=120\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SUPPORT_EMMC_BOOT=y\n CONFIG_SUN8I_EMAC=y\ndiff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig\nindex de46d205453..6a1af7f9b3a 100644\n--- a/configs/beelink_gs1_defconfig\n+++ b/configs/beelink_gs1_defconfig\n@@ -5,6 +5,9 @@ CONFIG_SPL=y\n CONFIG_MACH_SUN50I_H6=y\n CONFIG_SUNXI_DRAM_H6_LPDDR3=y\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=356\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_PSCI_RESET is not set\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_LED=y\ndiff --git a/configs/liontron-h-a133l_defconfig b/configs/liontron-h-a133l_defconfig\nindex 831d5b56e3a..f7bb994509f 100644\n--- a/configs/liontron-h-a133l_defconfig\n+++ b/configs/liontron-h-a133l_defconfig\n@@ -23,6 +23,9 @@ CONFIG_MACH_SUN50I_A133=y\n CONFIG_SUNXI_DRAM_A133_LPDDR4=y\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n CONFIG_R_I2C_ENABLE=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=240\n+# CONFIG_SPL_SUNXI_LED_STATUS_STATE is not set\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SPL_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig\nindex 6704a24a880..83bf0326bd4 100644\n--- a/configs/nanopi_neo2_defconfig\n+++ b/configs/nanopi_neo2_defconfig\n@@ -6,6 +6,9 @@ CONFIG_SPL=y\n CONFIG_MACH_SUN50I_H5=y\n CONFIG_DRAM_ZQ=3881977\n # CONFIG_DRAM_ODT_EN is not set\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=362\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SUN8I_EMAC=y\n CONFIG_USB_EHCI_HCD=y\ndiff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig\nindex e80e32a63d4..024301f990c 100644\n--- a/configs/nanopi_neo_plus2_defconfig\n+++ b/configs/nanopi_neo_plus2_defconfig\n@@ -7,6 +7,9 @@ CONFIG_MACH_SUN50I_H5=y\n CONFIG_DRAM_ZQ=3881977\n # CONFIG_DRAM_ODT_EN is not set\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=362\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SUN8I_EMAC=y\n CONFIG_USB_EHCI_HCD=y\ndiff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig\nindex 125137bc321..1fa1676e091 100644\n--- a/configs/orangepi_3_defconfig\n+++ b/configs/orangepi_3_defconfig\n@@ -6,6 +6,9 @@ CONFIG_MACH_SUN50I_H6=y\n CONFIG_SUNXI_DRAM_H6_LPDDR3=y\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n CONFIG_BLUETOOTH_DT_DEVICE_FIXUP=\"brcm,bcm4345c5\"\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=356\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_PHY_SUN50I_USB3=y\n CONFIG_USB_XHCI_HCD=y\ndiff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig\nindex 577f7436c15..10864827adf 100644\n--- a/configs/orangepi_lite2_defconfig\n+++ b/configs/orangepi_lite2_defconfig\n@@ -4,6 +4,9 @@ CONFIG_DEFAULT_DEVICE_TREE=\"sun50i-h6-orangepi-lite2\"\n CONFIG_SPL=y\n CONFIG_MACH_SUN50I_H6=y\n CONFIG_SUNXI_DRAM_H6_LPDDR3=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=356\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_PSCI_RESET is not set\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_USB_EHCI_HCD=y\ndiff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig\nindex d856a25814b..1e9a7cdaf7a 100644\n--- a/configs/orangepi_pc2_defconfig\n+++ b/configs/orangepi_pc2_defconfig\n@@ -6,6 +6,9 @@ CONFIG_SPL=y\n CONFIG_MACH_SUN50I_H5=y\n CONFIG_DRAM_ZQ=3881977\n CONFIG_SPL_SPI_SUNXI=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=362\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SPL_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig\nindex e93154cc0e9..7f622fe70f1 100644\n--- a/configs/orangepi_prime_defconfig\n+++ b/configs/orangepi_prime_defconfig\n@@ -6,6 +6,9 @@ CONFIG_SPL=y\n CONFIG_MACH_SUN50I_H5=y\n CONFIG_DRAM_ZQ=3881977\n # CONFIG_DRAM_ODT_EN is not set\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=362\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SUN8I_EMAC=y\n CONFIG_USB_EHCI_HCD=y\ndiff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig\nindex 831bfe66e25..942b751e181 100644\n--- a/configs/orangepi_zero2_defconfig\n+++ b/configs/orangepi_zero2_defconfig\n@@ -10,6 +10,9 @@ CONFIG_MACH_SUN50I_H616=y\n CONFIG_SUNXI_DRAM_H616_DDR3_1333=y\n CONFIG_R_I2C_ENABLE=y\n CONFIG_SPL_SPI_SUNXI=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=76\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SPL_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig\nindex c4d9800975c..945379533ab 100644\n--- a/configs/orangepi_zero_plus2_defconfig\n+++ b/configs/orangepi_zero_plus2_defconfig\n@@ -7,6 +7,9 @@ CONFIG_MACH_SUN50I_H5=y\n CONFIG_DRAM_ZQ=3881977\n # CONFIG_DRAM_ODT_EN is not set\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=362\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SUN8I_EMAC=y\n CONFIG_USB_EHCI_HCD=y\ndiff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig\nindex 4b6491dc846..2979c9f7f7b 100644\n--- a/configs/orangepi_zero_plus_defconfig\n+++ b/configs/orangepi_zero_plus_defconfig\n@@ -6,6 +6,9 @@ CONFIG_SPL=y\n CONFIG_MACH_SUN50I_H5=y\n CONFIG_DRAM_ZQ=3881977\n # CONFIG_DRAM_ODT_EN is not set\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=362\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SUN8I_EMAC=y\n CONFIG_USB_EHCI_HCD=y\ndiff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig\nindex 9d204ef5548..88e9a0879f7 100644\n--- a/configs/radxa-cubie-a5e_defconfig\n+++ b/configs/radxa-cubie-a5e_defconfig\n@@ -15,6 +15,9 @@ CONFIG_DRAM_SUNXI_TPR12=0x3533302f\n CONFIG_MACH_SUN55I_A523=y\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n CONFIG_R_I2C_ENABLE=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=356\n+# CONFIG_SPL_SUNXI_LED_STATUS_STATE is not set\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SPL_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig\nindex 1bd167ce0f6..0b5c57b93b9 100644\n--- a/configs/tanix_tx1_defconfig\n+++ b/configs/tanix_tx1_defconfig\n@@ -14,6 +14,9 @@ CONFIG_MACH_SUN50I_H616=y\n CONFIG_SUNXI_DRAM_H616_LPDDR3=y\n CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n CONFIG_R_I2C_ENABLE=y\n+CONFIG_SPL_SUNXI_LED_STATUS=y\n+CONFIG_SPL_SUNXI_LED_STATUS_BIT=231\n+CONFIG_SPL_SUNXI_LED_STATUS_STATE=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n CONFIG_SPL_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n","prefixes":["3/3"]}