{"id":2220024,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2220024/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260405195927.2837914-2-simons.philippe@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260405195927.2837914-2-simons.philippe@gmail.com>","list_archive_url":null,"date":"2026-04-05T19:59:26","name":"[1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"46617f72fedffa2c2f6255e1c4b66147b41c65bb","submitter":{"id":88794,"url":"http://patchwork.ozlabs.org/api/1.2/people/88794/?format=json","name":"Philippe Simons","email":"simons.philippe@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260405195927.2837914-2-simons.philippe@gmail.com/mbox/","series":[{"id":498807,"url":"http://patchwork.ozlabs.org/api/1.2/series/498807/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=498807","date":"2026-04-05T19:59:25","name":"Fix LPDDR3 H616 TPR6 parsing","version":1,"mbox":"http://patchwork.ozlabs.org/series/498807/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220024/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220024/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=RsQ3Oboq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Proper order from LSB to MSB is DDR3, DDR4,\nLPDDR3 and LPDDR4\n\nFix that.\n\nSigned-off-by: Jernej Skrabec \n[adjusted commit message]\nSigned-off-by: Philippe Simons \n---\n arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c\nindex 3345c9b8e82..42a0550e015 100644\n--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c\n+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c\n@@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para,\n \t\tval = para->tpr6 & 0xff;\n \t\tbreak;\n \tcase SUNXI_DRAM_TYPE_LPDDR3:\n-\t\tval = para->tpr6 >> 8 & 0xff;\n+\t\tval = para->tpr6 >> 16 & 0xff;\n \t\tbreak;\n \tcase SUNXI_DRAM_TYPE_LPDDR4:\n \t\tval = para->tpr6 >> 24 & 0xff;\n","prefixes":["1/2"]}