{"id":2217831,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2217831/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-8-aswin.murugan@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260330171419.1117817-8-aswin.murugan@oss.qualcomm.com>","list_archive_url":null,"date":"2026-03-30T17:14:19","name":"[v3,7/7] misc: update API documentation for bit field support in NVMEM","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"7729e5a0e8a1c54c6b6659f7fd6718b861bacfa0","submitter":{"id":90811,"url":"http://patchwork.ozlabs.org/api/1.2/people/90811/?format=json","name":"Aswin Murugan","email":"aswin.murugan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.2/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-8-aswin.murugan@oss.qualcomm.com/mbox/","series":[{"id":498069,"url":"http://patchwork.ozlabs.org/api/1.2/series/498069/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=498069","date":"2026-03-30T17:14:12","name":"qcom: Add NVMEM bitfield support and reboot���mode integration","version":3,"mbox":"http://patchwork.ozlabs.org/series/498069/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2217831/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2217831/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=DHgXXODi;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=fQBqqjYB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"DHgXXODi\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"fQBqqjYB\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkyZW2nTXz1yG7\n\tfor ; Tue, 31 Mar 2026 04:16:03 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 10FB384035;\n\tMon, 30 Mar 2026 19:15:42 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id F417184035; Mon, 30 Mar 2026 19:15:40 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id C9DBF83F5B\n for ; Mon, 30 Mar 2026 19:15:38 +0200 (CEST)","from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 62UF2IMX3721837\n for ; Mon, 30 Mar 2026 17:15:37 GMT","from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d7pvmssk5-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Mon, 30 Mar 2026 17:15:37 +0000 (GMT)","by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-82c8768a633so7980481b3a.2\n for ; Mon, 30 Mar 2026 10:15:37 -0700 (PDT)","from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, ilias.apalodimas@linaro.org, gchan9527@gmail.com,\n mkorpershoek@kernel.org, hs@nabladev.com,\n marek.vasut+renesas@mailbox.org, msp@baylibre.com,\n dinesh.maniyam@altera.com, peng.fan@nxp.com, quentin.schulz@cherry.de,\n kever.yang@rock-chips.com, jamie.gibbons@microchip.com,\n justin@tidylabs.net, xypron.glpk@gmx.de, n-francis@ti.com, h-vm@ti.com,\n ycliang@andestech.com, u-boot@lists.denx.de, u-boot-qcom@groups.io","Subject":"[PATCH v3 7/7] misc: update API documentation for bit field support\n in NVMEM","Date":"Mon, 30 Mar 2026 22:44:19 +0530","Message-Id":"<20260330171419.1117817-8-aswin.murugan@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>","References":"<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-GUID":"paoe-E8KmeWVYPhdP3qAG6sCbSS7UtBu","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwMzMwMDE0MSBTYWx0ZWRfX9NS31xipWssj\n tLD9j7+Fq7BDCnKEwxMq5Q19Fess1Lb01VumT2ojvxX+xfI5ekhyYjdWe8LJMnNO9kX/ipIUytH\n f0QC5xw7JDrJU+NduJHETPVDRjnT2UsWRVsNLZa3zkXyJ9j6Voq8YIzAsnC5zvJUHB8OJNcK5hM\n rTsFuDyKdh1PxnCPBJyh8FNseXla76ohP6aagYIk3vLLMw0cDCxbVqrMmGKBam5WRbGYTtqZlPW\n WdnWa9v5t+Evl474vCKhMv+M1N+gD9sJjN14bJExg5RY/bzIiC5jn3wCPHSgpYcun3Bj66WABHo\n wR+gaCxD6gsyWGr9aH0kJy0idpvjHlIoIne5URZxHGVKkn1od+6TaiIDkWRWRDZXBB3+YJ550BK\n ZUlKgXvwPAvoNwNlj5GTXj8tfZG5VNwzdlUfmXMgC1HZfB3xdZtsPJG09yzQTYi6ztr7w4/mX/K\n f4ARRgzy2Hb2AHclrIg==","X-Proofpoint-ORIG-GUID":"paoe-E8KmeWVYPhdP3qAG6sCbSS7UtBu","X-Authority-Analysis":"v=2.4 cv=S9rUAYsP c=1 sm=1 tr=0 ts=69caafb9 cx=c_pps\n a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8\n a=FN49bKHmwJfEaFta7s4A:9 a=OpyuDcXvxspvyRM73sMx:22","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 spamscore=0\n suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501\n impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2603300141","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Update the nvmem_cell_read() and nvmem_cell_write() documentation to\ndescribe the new bit field operation mode.\n\nThe documentation now clearly explains:\n\nFor bit field mode (nbits > 0):\n- Read: extracts the bit field from raw hardware bytes\n- Write: performs read-modify-write to preserve other bits\n- Requirements: buffer size must be sizeof(u32), cell size <= 4 bytes\n\nFor non-bit-field mode (nbits == 0):\n- Read/Write: direct byte-level access\n- Requirements: buffer size must equal the cell size\n\nThis helps developers understand when to use each mode and the\nassociated buffer size requirements.\n\nSigned-off-by: Aswin Murugan \n---\n include/nvmem.h | 24 ++++++++++++++++++++++--\n 1 file changed, 22 insertions(+), 2 deletions(-)","diff":"diff --git a/include/nvmem.h b/include/nvmem.h\nindex dd82122f16f..af1d2594bd6 100644\n--- a/include/nvmem.h\n+++ b/include/nvmem.h\n@@ -47,9 +47,19 @@ struct udevice;\n * @buf: The buffer to read into\n * @size: The size of @buf\n *\n+ * For cells with bit fields (nbits > 0), this function:\n+ * - Reads the raw bytes from hardware\n+ * - Extracts the bit field using bit_offset and nbits\n+ * - Returns the extracted value in @buf\n+ * - Requires @size == sizeof(u32) and @cell->size <= 4\n+ *\n+ * For cells without bit fields (nbits == 0):\n+ * - Reads raw bytes directly\n+ * - Requires @size == @cell->size\n+ *\n * Return:\n * * 0 on success\n- * * -EINVAL if @buf is not the same size as @cell.\n+ * * -EINVAL if @size doesn't match requirements\n * * -ENOSYS if CONFIG_NVMEM is disabled\n * * A negative error if there was a problem reading the underlying storage\n */\n@@ -61,9 +71,19 @@ int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size);\n * @buf: The buffer to write from\n * @size: The size of @buf\n *\n+ * For cells with bit fields (nbits > 0), this function:\n+ * - Performs Read-Modify-Write to preserve other bits\n+ * - Masks and shifts the value to the correct bit position\n+ * - Merges with existing bits outside the field\n+ * - Requires @size == sizeof(u32) and @cell->size <= 4\n+ *\n+ * For cells without bit fields (nbits == 0):\n+ * - Writes raw bytes directly\n+ * - Requires @size == @cell->size\n+ *\n * Return:\n * * 0 on success\n- * * -EINVAL if @buf is not the same size as @cell\n+ * * -EINVAL if @size doesn't match requirements\n * * -ENOSYS if @cell is read-only, or if CONFIG_NVMEM is disabled\n * * A negative error if there was a problem writing the underlying storage\n */\n","prefixes":["v3","7/7"]}