{"id":2217827,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2217827/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-4-aswin.murugan@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260330171419.1117817-4-aswin.murugan@oss.qualcomm.com>","list_archive_url":null,"date":"2026-03-30T17:14:15","name":"[v3,3/7] mach-snapdragon: Integrate reboot-mode handling","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"f4df24b5bcfb5b4679213c0d0d5eae7c1d2de9e5","submitter":{"id":90811,"url":"http://patchwork.ozlabs.org/api/1.2/people/90811/?format=json","name":"Aswin Murugan","email":"aswin.murugan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.2/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-4-aswin.murugan@oss.qualcomm.com/mbox/","series":[{"id":498069,"url":"http://patchwork.ozlabs.org/api/1.2/series/498069/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=498069","date":"2026-03-30T17:14:12","name":"qcom: Add NVMEM bitfield support and reboot���mode integration","version":3,"mbox":"http://patchwork.ozlabs.org/series/498069/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2217827/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2217827/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=hQwNvYTa;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=FULmdP6L;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"hQwNvYTa\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"FULmdP6L\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkyYg3pMYz1yG7\n\tfor ; Tue, 31 Mar 2026 04:15:19 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 9703B84020;\n\tMon, 30 Mar 2026 19:15:11 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id 6BF6E84020; Mon, 30 Mar 2026 19:15:10 +0200 (CEST)","from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 2711F83E7A\n for ; Mon, 30 Mar 2026 19:15:07 +0200 (CEST)","from pps.filterd (m0279863.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 62UG48AG3668463\n for ; Mon, 30 Mar 2026 17:15:06 GMT","from mail-pj1-f71.google.com (mail-pj1-f71.google.com\n [209.85.216.71])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d7vcc09pv-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Mon, 30 Mar 2026 17:15:06 +0000 (GMT)","by mail-pj1-f71.google.com with SMTP id\n 98e67ed59e1d1-35da99b90f6so1762646a91.1\n for ; Mon, 30 Mar 2026 10:15:06 -0700 (PDT)","from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, ilias.apalodimas@linaro.org, gchan9527@gmail.com,\n mkorpershoek@kernel.org, hs@nabladev.com,\n marek.vasut+renesas@mailbox.org, msp@baylibre.com,\n dinesh.maniyam@altera.com, peng.fan@nxp.com, quentin.schulz@cherry.de,\n kever.yang@rock-chips.com, jamie.gibbons@microchip.com,\n justin@tidylabs.net, xypron.glpk@gmx.de, n-francis@ti.com, h-vm@ti.com,\n ycliang@andestech.com, u-boot@lists.denx.de, u-boot-qcom@groups.io","Subject":"[PATCH v3 3/7] mach-snapdragon: Integrate reboot-mode handling","Date":"Mon, 30 Mar 2026 22:44:15 +0530","Message-Id":"<20260330171419.1117817-4-aswin.murugan@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>","References":"<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"iWxCHupHK7_-__G2fY1MGCDRqLYODdI6","X-Authority-Analysis":"v=2.4 cv=GbMaXAXL c=1 sm=1 tr=0 ts=69caaf9a cx=c_pps\n a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8\n a=zRlt6gtmhGCAqZgH310A:9 a=uKXjsCUrEbL0IQVhDsJ9:22","X-Proofpoint-GUID":"iWxCHupHK7_-__G2fY1MGCDRqLYODdI6","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwMzMwMDE0MCBTYWx0ZWRfX/NSq0aatIwMS\n EX5xj3ZeV9N5DU5QHDOxzxtpYxnjPXupgu+ZK24QG7iiyRNSmBfdzP6yFDV3+QmE7iwa+nGUnOH\n GzOj7YAHD4+RDFYvgkYOeR2bUQ/0z9zdmaFFxNar9xMxv7TRBW/5b+mt/VVpEfUv/oCw/7ZsgqK\n WN+XrLUh5NRH+APFhIft2id/G2W0Mww4icoRsRVbFVx1z0kn8gieI+nRzrOumlfEDlAAvGB4Pdj\n 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","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add reboot-mode detection and automatic fastboot entry to Qualcomm board\ninitialization. This enables 'reboot bootloader' functionality on\nplatforms with reboot-mode device tree configuration.\n\nChanges:\n- Add qcom_handle_reboot_mode() call in board_late_init()\n- Conditionally compile with CONFIG_DM_REBOOT_MODE\n- Reorganize header includes\n\nSigned-off-by: Aswin Murugan \n---\nChanges in v3:\n1. No change in v3\n---\n arch/arm/mach-snapdragon/board.c | 56 +++++++++++++++++++++++++-------\n 1 file changed, 45 insertions(+), 11 deletions(-)","diff":"diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\nindex 5fb3240acc5..a596d052711 100644\n--- a/arch/arm/mach-snapdragon/board.c\n+++ b/arch/arm/mach-snapdragon/board.c\n@@ -9,6 +9,15 @@\n #define LOG_CATEGORY LOGC_BOARD\n #define pr_fmt(fmt) \"QCOM: \" fmt\n \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n #include \n #include \n #include \n@@ -16,22 +25,14 @@\n #include \n #include \n #include \n-#include \n #include \n-#include \n-#include \n-#include \n-#include \n+#include \n #include \n #include \n #include \n #include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n+#include \n+#include \n \n #include \"qcom-priv.h\"\n \n@@ -506,6 +507,33 @@ void qcom_show_boot_source(void)\n \tenv_set(\"boot_source\", name);\n }\n \n+/**\n+ * qcom_handle_reboot_mode() - Process reboot-mode detection and handle fastboot entry\n+ *\n+ * This function detects the reboot reason from PMIC registers and automatically\n+ * enters fastboot mode if the reboot reason was \"bootloader\".\n+ */\n+static void qcom_handle_reboot_mode(void)\n+{\n+\tstruct udevice *reboot_dev;\n+\tconst char *reboot_mode;\n+\tint ret;\n+\n+\tret = uclass_first_device_err(UCLASS_REBOOT_MODE, &reboot_dev);\n+\tif (ret)\n+\t\treturn;\n+\n+\tret = dm_reboot_mode_update(reboot_dev);\n+\tif (ret)\n+\t\treturn;\n+\n+\treboot_mode = env_get(\"reboot-mode\");\n+\tif (reboot_mode && !strcmp(reboot_mode, \"bootloader\")) {\n+\t\tprintf(\"Entering fastboot mode due to reboot reason...\\n\");\n+\t\trun_command(\"run fastboot\", 0);\n+\t}\n+}\n+\n void __weak qcom_late_init(void)\n {\n }\n@@ -570,6 +598,12 @@ int board_late_init(void)\n \tqcom_late_init();\n \n \tqcom_show_boot_source();\n+\n+\t/* Handle reboot-mode detection and fastboot entry */\n+#if IS_ENABLED(CONFIG_DM_REBOOT_MODE)\n+\tqcom_handle_reboot_mode();\n+#endif\n+\n \t/* Configure the dfu_string for capsule updates */\n \tqcom_configure_capsule_updates();\n \n","prefixes":["v3","3/7"]}