{"id":2235221,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2235221/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260508034912.4082520-1-rkannoth@marvell.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.2/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508034912.4082520-1-rkannoth@marvell.com>","list_archive_url":null,"date":"2026-05-08T03:49:03","name":"[v12,net-next,0/9] octeontx2-af: npc: Enhancements.","submitter":{"id":86908,"url":"http://patchwork.ozlabs.org/api/1.2/people/86908/?format=json","name":"Ratheesh Kannoth","email":"rkannoth@marvell.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260508034912.4082520-1-rkannoth@marvell.com/mbox/","series":[{"id":503453,"url":"http://patchwork.ozlabs.org/api/1.2/series/503453/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=503453","date":"2026-05-08T03:49:12","name":"octeontx2-af: npc: Enhancements.","version":12,"mbox":"http://patchwork.ozlabs.org/series/503453/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2235221/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=n0/2h+bG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.137; helo=smtp4.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp4.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gC3F20KRfz1yCg\n\tfor ; Sat, 09 May 2026 08:09:26 +1000 (AEST)","from localhost (localhost [127.0.0.1])\n\tby smtp4.osuosl.org (Postfix) with ESMTP id BC291410EA;\n\tFri, 8 May 2026 22:09:19 +0000 (UTC)","from smtp4.osuosl.org ([127.0.0.1])\n by localhost (smtp4.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id UqHhr0xP-55u; Fri, 8 May 2026 22:09:14 +0000 (UTC)","from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142])\n\tby smtp4.osuosl.org (Postfix) with ESMTP id E921D410EC;\n\tFri, 8 May 2026 22:09:13 +0000 (UTC)","from smtp2.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n by lists1.osuosl.org (Postfix) with ESMTP id B7B12358\n for ; Fri, 8 May 2026 04:07:51 +0000 (UTC)","from localhost (localhost [127.0.0.1])\n by smtp2.osuosl.org (Postfix) with ESMTP id B56ED409D6\n for ; Fri, 8 May 2026 04:07:51 +0000 (UTC)","from smtp2.osuosl.org ([127.0.0.1])\n by localhost (smtp2.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id yhiD_hHZ8SG7 for ;\n Fri, 8 May 2026 04:07:50 +0000 (UTC)","from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by smtp2.osuosl.org (Postfix) with ESMTPS id A974E404A0\n for ; Fri, 8 May 2026 04:07:50 +0000 (UTC)","from pps.filterd (m0431383.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 647NVKu02841680; Thu, 7 May 2026 20:49:30 -0700","from dc6wp-exch02.marvell.com ([4.21.29.225])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4e14g0gjd3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Thu, 07 May 2026 20:49:30 -0700 (PDT)","from DC6WP-EXCH02.marvell.com (10.76.176.209) by\n DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.25; Thu, 7 May 2026 20:49:29 -0700","from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com\n (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend\n Transport; Thu, 7 May 2026 20:49:29 -0700","from rkannoth-OptiPlex-7090.. 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MCAM enable state is tracked in a\nbitmap updated from the CN20K enable path.\n\nPatch 2 reduces stack usage in mlx5e_pcie_cong_get_thresh_config() by\nreusing a single union devlink_param_value and a local result struct\ninstead of holding a large array of unions on the stack, so the helper\nstays under the frame-size warning limit as the union grows (patches 3-4).\n\nPatch 3 changes devlink_nl_param_value_put() and\ndevlink_nl_param_value_fill_one() to pass union devlink_param_value by\npointer instead of by value. Passing two copies of the union by value in\nthe param netlink path consumes over 500 bytes of argument stack and risks\nCONFIG_FRAME_WARN as the union grows beyond its historical size (patch 4).\n\nPatch 4 (Saeed) introduces DEVLINK_PARAM_TYPE_U64_ARRAY and nested\nDEVLINK_ATTR_PARAM_VALUE_DATA attributes so drivers and user space can\nexchange bounded u64 arrays; YAML, uapi, and netlink validation are\nupdated.\n\nPatch 5 adds a runtime devlink parameter srch_order to reorder CN20K\nsubbank search during MCAM allocation.\n\nPatch 6 ties default MCAM entries to NIX LF alloc/free on CN20K, adds\nNIX_LF_DONT_FREE_DFT_IDXS for PF teardown paths that must not drop default\nNPC indexes while the driver still owns state, and tightens nix_lf_alloc\nerror propagation.\n\nPatch 7 allows loading a custom KPU profile from /lib/firmware/kpu via\nmodule parameter kpu_profile, with cam2 / ptype_mask wiring and helpers\nthat share firmware-sourced vs filesystem-sourced profile layouts.\n\nPatch 8 makes default-rule allocation, AF flow install, and PF-side RSS,\ndefaults, and ethtool flows respect the active CN20K MCAM keyword width\n(X2 vs X4), including X4 reference-index masking and -EOPNOTSUPP when a\nflow needs X4 keys on an X2-only profile.\n\nPatch 9 replaces file-scope npc_priv and static dstats with allocation\nsized from discovered bank/subbank geometry, threads npc_priv_get()\nthrough CN20K NPC paths, and allocates dstats via devm_kzalloc for the\ndebugfs helper.\n\nThe mlx5 change sits immediately before the devlink patches so the series\napplies cleanly and stays warning-free when built incrementally;\npass-by-pointer precedes the U64 array type so helpers are not copying an\neven larger union by value. The CN20K patches keep srch_order ahead of\nNIX LF coordination, KPU-from-filesystem, X2/X4 handling, and the npc_priv\nrefactor that touches the same files heavily.\n\nRatheesh Kannoth (8):\n octeontx2-af: npc: cn20k: debugfs enhancements\n net/mlx5e: trim stack use in PCIe congestion threshold helper\n devlink: pass param values by pointer\n octeontx2-af: npc: cn20k: add subbank search order control\n octeontx2: cn20k: Coordinate default rules with NIX LF lifecycle\n octeontx2-af: npc: Support for custom KPU profile from filesystem\n octeontx2: cn20k: Respect NPC MCAM X2/X4 profile in flows and DFT\n alloc\n octeontx2-af: npc: cn20k: Allocate npc_priv and dstats dynamically.\n\nSaeed Mahameed (1):\n devlink: Implement devlink param multi attribute nested data values\n\n Documentation/netlink/specs/devlink.yaml | 4 +\n drivers/dpll/zl3073x/devlink.c | 6 ++-\n drivers/net/ethernet/amazon/ena/ena_devlink.c | 8 ++-\n drivers/net/ethernet/amd/pds_core/core.h | 2 ++-\n drivers/net/ethernet/amd/pds_core/devlink.c | 2 ++-\n drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c | 6 ++-\n drivers/net/ethernet/intel/ice/devlink/devlink.c | 30 ++-\n .../ethernet/marvell/octeontx2/af/cn20k/debugfs.c | 175 ++++-\n .../net/ethernet/marvell/octeontx2/af/cn20k/npc.c | 545 ++++++++-----\n .../net/ethernet/marvell/octeontx2/af/cn20k/npc.h | 13 +++-\n drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 1 +\n drivers/net/ethernet/marvell/octeontx2/af/npc.h | 17 +\n drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 12 ++-\n ...et/ethernet/marvell/octeontx2/af/rvu_devlink.c | 114 ++-\n ...rs/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 69 ++-\n ...rs/net/ethernet/marvell/octeontx2/af/rvu_npc.c | 478 +++++++++--\n ...rs/net/ethernet/marvell/octeontx2/af/rvu_npc.h | 17 +\n ...net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c | 12 +++-\n ...rs/net/ethernet/marvell/octeontx2/af/rvu_reg.h | 1 +\n .../ethernet/marvell/octeontx2/nic/otx2_devlink.c | 4 ++-\n ...et/ethernet/marvell/octeontx2/nic/otx2_flows.c | 48 ++-\n ...s/net/ethernet/marvell/octeontx2/nic/otx2_pf.c | 6 +--\n drivers/net/ethernet/mellanox/mlx4/main.c | 14 ++-\n drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 72 ++-\n ...hernet/mellanox/mlx5/core/en/pcie_cong_event.c | 36 ++-\n ...ethernet/mellanox/mlx5/core/eswitch_offloads.c | 2 ++-\n drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 4 ++-\n ...net/ethernet/mellanox/mlx5/core/lib/nv_param.c | 12 ++-\n drivers/net/ethernet/mellanox/mlxsw/core.c | 8 ++-\n ...ers/net/ethernet/netronome/nfp/devlink_param.c | 6 ++-\n drivers/net/netdevsim/dev.c | 4 ++-\n include/net/devlink.h | 12 ++-\n include/uapi/linux/devlink.h | 1 +\n net/devlink/netlink_gen.c | 2 +\n net/devlink/param.c | 120 ++-\n\n 35 files changed, 1315 insertions(+), 548 deletions(-)\n\n--\n\nv11 -> v12: Addressed Paolo,Jiri comments.\n\thttps://lore.kernel.org/netdev/20260409025055.1664053-1-rkannoth@marvell.com/\n\tAdded one patch which was rejected by simon in net (as it was kind of enhancement rather than a bug)\n\tAdded one more patch- which allocates two variables from heap.\n\nv10 -> v11: Addressed Paolo comments.\n\thttps://lore.kernel.org/netdev/20260403025533.6250-1-rkannoth@marvell.com/\n\nv9 -> v10: Addressed Paolo comments\n\thttps://lore.kernel.org/netdev/\n\t20260330053105.2722453-1-rkannoth@marvell.com/\n\nv8 -> v9: Addressed Simon comments\n\thttps://lore.kernel.org/netdev/\n\t20260325072159.1126964-1-rkannoth@marvell.com/\n\nv7 -> v8: Addressed Simon comments\n\thttps://lore.kernel.org/netdev/\n\t20260323035110.3908741-1-rkannoth@marvell.com/T/#t\n\nv6 -> v7: Addressed Simon comments\n\thttps://lore.kernel.org/netdev/20260320165432.98832-1-horms@kernel.org/\n\nv5 -> v6: Addressed Jakub,Jiri comments\n\thttps://lore.kernel.org/netdev/\n\t20260317045623.250187-1-rkannoth@marvell.com/\n\nv4 -> v5: Addressed Jakub comments\n\thttps://lore.kernel.org/netdev/\n\t20260312022754.2029595-6-rkannoth@marvell.com/\n\nv3 -> v4: Addressed Simon comments\n\thttps://lore.kernel.org/netdev/abDeXLpMMxp7G1v3@rkannoth-OptiPlex-7090/#t\n\nv2 -> v3: Addressed Simon comments.\n\thttps://lore.kernel.org/netdev/\n\t20260304043032.3661647-1-rkannoth@marvell.com/\n\nv1 -> v2: Addressed Jakub comments.\n\thttps://lore.kernel.org/netdev/\n\t20260302085803.2449828-1-rkannoth@marvell.com/#t\n\n2.43.0"}