{"id":2234714,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2234714/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com>","list_archive_url":null,"date":"2026-05-08T01:02:13","name":"[0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC","submitter":{"id":93362,"url":"http://patchwork.ozlabs.org/api/1.2/people/93362/?format=json","name":"Matthew Leung","email":"matthew.leung@oss.qualcomm.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com/mbox/","series":[{"id":503303,"url":"http://patchwork.ozlabs.org/api/1.2/series/503303/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=503303","date":"2026-05-08T01:02:13","name":"PCI: qcom: Add PCIe support for upcoming Hawi SoC","version":1,"mbox":"http://patchwork.ozlabs.org/series/503303/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2234714/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Dk4DyBCo;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Q6STFuf0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54143-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"Dk4DyBCo\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"Q6STFuf0\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBW7J4ljmz1yCg\n\tfor ; Fri, 08 May 2026 11:02:36 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 387EE301E5A7\n\tfor ; Fri, 8 May 2026 01:02:33 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 9D4E31EB1AA;\n\tFri, 8 May 2026 01:02:32 +0000 (UTC)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 489602F8E8F\n\tfor ; Fri, 8 May 2026 01:02:31 +0000 (UTC)","from pps.filterd (m0279871.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 647Kmj1n1424449\n\tfor ; Fri, 8 May 2026 01:02:30 GMT","from mail-dy1-f198.google.com (mail-dy1-f198.google.com\n [74.125.82.198])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e0pqfup24-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor ; Fri, 08 May 2026 01:02:30 +0000 (GMT)","by mail-dy1-f198.google.com with SMTP id\n 5a478bee46e88-2ef37c3f773so1735272eec.1\n for ; Thu, 07 May 2026 18:02:30 -0700 (PDT)","from [169.254.0.3] (Global_NAT1.qualcomm.com. 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a=ed25519;\n pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o=","X-Authority-Analysis":"v=2.4 cv=TJB1jVla c=1 sm=1 tr=0 ts=69fd3626 cx=c_pps\n a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22\n a=EUspDBNiAAAA:8 a=DYLwrDP1oi7eDBu46k8A:9 a=QEXdDO2ut3YA:10\n a=bBxd6f-gb0O0v-kibOvt:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNTA4MDAwNyBTYWx0ZWRfX/MEXldKXgQXG\n 35VUoyJQSHeyfoSW5M5DeDearDrjbwO0UQeJZyWMjk8VQn3MddjcrLEM+yO1JqSPIwGpIRFeizU\n v5GQY2ZBpJnNmKgUxyuY5wU2Ogxe9pW3tO8f+d1Xa7ncCKTwyrReXr9felfaK1cZxFa2rFO7OkJ\n ToxvTi1zpQDmYFJUps9nNIdXGKj8t/+LFIyEQz/FWjfddJ+8kiAgCy/clTrbY/SOGlNJ8iIaM0A\n 4FmLuuL4HZrckcScPWEKJSG0MB/3XZor+r68R+Hac7OGeUZAzhqJoW7TzDWN2YRP4et/QXORR/a\n 8/4yCmpjAuf0e1oXrGiDD15DYidwQHP6JkPP7MGZ8+tMc1tbtdkVoTzJhqp3lmC6iRm1ulrUToH\n STucbmydibo9rU3Z6fjgL4KnmYityoDptygF61xTC8THvutbyfGBKIaUR1a12iWpTFjmvWIdpfY\n T2WMpS0TyuwlPGKaHwg==","X-Proofpoint-GUID":"XREr2SdHfbyqA76WqgsVg5Mzalhl128c","X-Proofpoint-ORIG-GUID":"XREr2SdHfbyqA76WqgsVg5Mzalhl128c","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n clxscore=1011 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0\n phishscore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080007"},"content":"This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi\nplatform features two PCIe controllers: one capable of Gen3 x2 operation\nand one capable of Gen4 x1 operation. The first patch adds the device\ntree bindings documentation for the Hawi PCIe controller, and the second\npatch adds driver support by enabling the Hawi compatible string in the\nexisting qcom PCIe driver.\n\nThis series depends on the following prerequisite series:\n- [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the\n upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)\n- [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC\n (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)\n\nThese dependencies add necessary headers for running dt_binding_check\nagainst the binding.\n\nSigned-off-by: Matthew Leung \n---\nMatthew Leung (2):\n dt-bindings: PCI: qcom: Document the Hawi PCIe Controller\n PCI: qcom: Add support for Hawi\n\n .../devicetree/bindings/pci/qcom,hawi-pcie.yaml | 188 +++++++++++++++++++++\n drivers/pci/controller/dwc/pcie-qcom.c | 1 +\n 2 files changed, 189 insertions(+)\n---\nbase-commit: 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0\nchange-id: 20260506-hawi-pcie-f61435ca420c\nprerequisite-change-id: 20260316-clk-hawi-1ad4cad36d6a:v3\nprerequisite-patch-id: c4fbb0620d748d7f1ee675ade5167775bd31c8ac\nprerequisite-patch-id: ae5e212518cc333a1a93564cabfc6abd128df664\nprerequisite-patch-id: 3c3816e0d595589fc02383f10e48c83a61fdc9d1\nprerequisite-patch-id: cbc13fb819d1c1ee77957393f0958f05db8db864\nprerequisite-patch-id: 17e2c0cfbbea826fefa1c67d0f5dc2094ab73d76\nprerequisite-patch-id: 150dc74750377f4558deab6b179632872bcbb71c\nprerequisite-patch-id: 38fe0da5b18610aeb32c7154f9e50187ccaec6a4\nprerequisite-change-id: 20260311-icc-hawi-d6dc165f8935:v4\nprerequisite-patch-id: a1ff655f0b21d6259b158ad9f99a95bde31257e6\nprerequisite-patch-id: db21b6b20451be8475129faece7ef4191d41273c\n\nBest regards,\n-- \nMatthew Leung "}