{"id":2234637,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2234637/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260507234413.643512-1-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507234413.643512-1-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-05-07T23:43:13","name":"[v4,00/60] target/arm: Implement FEAT_FP8","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260507234413.643512-1-richard.henderson@linaro.org/mbox/","series":[{"id":503296,"url":"http://patchwork.ozlabs.org/api/1.2/series/503296/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296","date":"2026-05-07T23:43:14","name":"target/arm: Implement FEAT_FP8","version":4,"mbox":"http://patchwork.ozlabs.org/series/503296/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2234637/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=lqN6O4Px;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Based-on: 20260507160959.449170-1-richard.henderson@linaro.org\n(\"[PATCH v3 00/11] fpu: Export some internals for targets\")\n\nChanges for v4:\n - TF-A firmware update for FEAT_FPMR\n - Rewrite decode/encode of FP8 data types\n - Rewrite FEAT_FP8FMA helpers\n - Enable FEAT_FP8DOT{4,2}\n - Enable FEAT_FP8F{32,16}MM\n\nThis completes the set of 8-bit floating point features.\n\n\nr~\n\n\nPierrick Bouvier (1):\n tests/functional/aarch64/rme: update images to support FEAT_FP8\n\nRichard Henderson (59):\n target/arm: Implement ID_AA64ISAR3\n target/arm: Implement FEAT_FAMINMAX for AdvSIMD\n target/arm: Implement FEAT_FAMINMAX for SME\n target/arm: Implement FEAT_FAMINMAX for SVE\n target/arm: Enable FEAT_FAMINMAX for -cpu max\n target/arm: Update SCR bits for Arm ARM M.a.a\n target/arm: Update HCRX bits for Arm ARM M.a.a\n target/arm: Introduce FPMR\n target/arm: Update SCTLR bits for FEAT_FPMR\n target/arm: Enable EnFPM bits for FEAT_FPMR\n target/arm: Clear FPMR on ResetSVEState\n target/arm: Add FPMR_EL to TBFLAGS\n target/arm: Trap direct acceses to FPMR\n target/arm: Enable FEAT_FPMR for -cpu max\n target/arm: Implement ID_AA64FPFR0\n target/arm: Add isar_feature_aa64_f8cvt\n target/arm: Implement FSCALE for AdvSIMD\n target/arm: Implement FSCALE for SME\n target/arm: Split vector-type.h from cpu.h\n target/arm: Move vectors_overlap to vec_internal.h\n target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD\n target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE\n target/arm: Rename SME BFCVT patterns to BFCVT_hs\n target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME\n target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD\n target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE\n target/arm: Implement F1CVT, F1CVTL, F2CVT, F2CVTL for SME\n target/arm: Implement BFCVTN for SVE\n target/arm: Implement FCVTN (16- to 8-bit fp) for AdvSIMD\n target/arm: Implement FCVTN, FCVTN2 (32- to 8-bit fp) for AdvSIMD\n target/arm: Implement FCVTN (16- to 8-bit fp) for SVE\n target/arm: Implement FCVTNB, FCVTNT for SVE\n target/arm: Implement FCVT (FP16 to FP8) for SME\n target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME\n target/arm: Implement LUTI2, LUTI4 for AdvSIMD\n target/arm: Implement LUTI2, LUTI4 for SVE\n target/arm: Enable FEAT_LUT for -cpu max\n target/arm: Enable FEAT_FP8 for -cpu max\n target/arm: Update ID_AA64SMFR0_EL1 fields to ARM M.b\n target/arm: Implement MOVT (vector to table)\n target/arm: Implement LUTI4 (four registers, 8-bit)\n target/arm: Enable FEAT_SME_LUTv2 for -cpu max\n target/arm: Implement FMLALB, FMLALT for AdvSIMD\n target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE\n target/arm: Implement FMLALL{BB,BT,TB,TT} for AdvSIMD\n target/arm: Implement FMLALL{BB,BT,TB,TT} for SVE\n target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max\n target/arm: Implement FDOT (FP8 to FP32) for AdvSIMD\n target/arm: Implement FDOT (FP8 to FP32) for SVE\n target/arm: Enable FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4 for -cpu max\n target/arm: Implement FDOT (FP8 to FP16) for AdvSIMD\n target/arm: Implement FDOT (FP8 to FP16) for SVE\n target/arm: Enable FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2 for -cpu max\n target/arm: Implement FMMLA (FP8 to FP32) for AdvSIMD\n target/arm: Implement FMMLA (FP8 to FP32) for SVE\n target/arm: Enable FEAT_F8F32MM for -cpu max\n target/arm: Implement FMMLA (FP8 to FP16) for AdvSIMD\n target/arm: Implement FMMLA (FP8 to FP16) for SVE\n target/arm: Enable FEAT_F8F16MM for -cpu max\n\n target/arm/cpregs.h | 5 +\n target/arm/cpu-features.h | 137 +++\n target/arm/cpu.h | 52 +-\n target/arm/helper-fp8.h | 14 +\n target/arm/internals.h | 13 +-\n target/arm/tcg/helper-a64-defs.h | 11 +\n target/arm/tcg/helper-defs.h | 6 +\n target/arm/tcg/helper-fp8-defs.h | 40 +\n target/arm/tcg/helper-sme-defs.h | 2 +-\n target/arm/tcg/helper-sve-defs.h | 14 +\n target/arm/tcg/translate-a64.h | 1 +\n target/arm/tcg/translate.h | 10 +\n target/arm/tcg/vec_internal.h | 19 +\n target/arm/vector-type.h | 44 +\n target/arm/helper.c | 43 +-\n target/arm/machine.c | 20 +\n target/arm/tcg/cpu64.c | 24 +\n target/arm/tcg/fp8_helper.c | 867 +++++++++++++++++++\n target/arm/tcg/hflags.c | 41 +\n target/arm/tcg/sme_helper.c | 8 +-\n target/arm/tcg/sve_helper.c | 8 +\n target/arm/tcg/translate-a64.c | 186 ++++\n target/arm/tcg/translate-sme.c | 109 ++-\n target/arm/tcg/translate-sve.c | 235 +++++\n target/arm/tcg/vec_helper.c | 66 ++\n target/arm/tcg/vec_helper64.c | 51 ++\n docs/system/arm/emulation.rst | 13 +\n target/arm/cpu-sysregs.h.inc | 2 +\n target/arm/tcg/a64.decode | 47 +\n target/arm/tcg/meson.build | 1 +\n target/arm/tcg/sme.decode | 36 +-\n target/arm/tcg/sve.decode | 50 +-\n tests/functional/aarch64/test_rme_sbsaref.py | 7 +-\n tests/functional/aarch64/test_rme_virt.py | 7 +-\n 34 files changed, 2124 insertions(+), 65 deletions(-)\n create mode 100644 target/arm/helper-fp8.h\n create mode 100644 target/arm/tcg/helper-fp8-defs.h\n create mode 100644 target/arm/vector-type.h\n create mode 100644 target/arm/tcg/fp8_helper.c"}