{"id":2234203,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2234203/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/cover/20260507113706.11400-1-fangyu.yu@linux.alibaba.com/","project":{"id":70,"url":"http://patchwork.ozlabs.org/api/1.2/projects/70/?format=json","name":"Linux KVM RISC-V","link_name":"kvm-riscv","list_id":"kvm-riscv.lists.infradead.org","list_email":"kvm-riscv@lists.infradead.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"http://lists.infradead.org/pipermail/kvm-riscv/","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507113706.11400-1-fangyu.yu@linux.alibaba.com>","list_archive_url":null,"date":"2026-05-07T11:36:56","name":"[RFC,v2,00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains","submitter":{"id":91416,"url":"http://patchwork.ozlabs.org/api/1.2/people/91416/?format=json","name":null,"email":"fangyu.yu@linux.alibaba.com"},"mbox":"http://patchwork.ozlabs.org/project/kvm-riscv/cover/20260507113706.11400-1-fangyu.yu@linux.alibaba.com/mbox/","series":[{"id":503164,"url":"http://patchwork.ozlabs.org/api/1.2/series/503164/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=503164","date":"2026-05-07T11:36:57","name":"iommu/riscv: Add hardware dirty tracking for second-stage domains","version":2,"mbox":"http://patchwork.ozlabs.org/series/503164/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2234203/comments/","headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=uw+BGk19;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=Y72oo2r4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Fangyu Yu The RISC-V\n IOMMU\n architecture defines an AMO_HWAD capability (Hardware Access/Dirty update)\n that allows the IOMMU to atomically set the A/D bits in second-stage PTEs\n on DMA access. When DC.tc.GADE is [...]\n Content analysis details: (-17.6 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [115.124.30.124 listed in list.dnswl.org]\n -7.5 USER_IN_DEF_DKIM_WL From: address is in the default DKIM welcome-list\n -7.5 USER_IN_DEF_SPF_WL From: address is in the default SPF welcome-list\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n -0.5 ENV_AND_HDR_SPF_MATCH Env and Hdr From used in default SPF WL Match\n 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay\n lines\n -0.0 DMARC_PASS DMARC pass policy","X-BeenThere":"kvm-riscv@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"kvm-riscv\" ","Errors-To":"kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"From: Fangyu Yu \n\nThe RISC-V IOMMU architecture defines an AMO_HWAD capability (Hardware\nAccess/Dirty update) that allows the IOMMU to atomically set the A/D bits\nin second-stage PTEs on DMA access. When DC.tc.GADE is asserted, the IOMMU\nautonomously sets D on the first write to a page mapped by an iohgatp\ndomain. This series wires that capability up to the iommufd dirty-tracking\ninterface (IOMMU_HWPT_SET_DIRTY_TRACKING / IOMMU_HWPT_GET_DIRTY_BITMAP) and\nreports IOMMU_CAP_DIRTY_TRACKING.\n\nDesign notes\n------------\n\n* The feature is scoped to second-stage (iohgatp) domains only; these are\n the domains created for KVM / VFIO device pass-through when userspace\n allocates an HWPT with IOMMU_HWPT_ALLOC_NEST_PARENT or\n IOMMU_HWPT_ALLOC_DIRTY_TRACKING. First-stage (iosatp) domains are not\n touched by this series.\n\n* The page-table side plugs into the existing generic_pt dirty hook\n framework (amdv1 / vtdss style). RISC-V adds the three required PTE\n ops – is_write_dirty / make_write_clean / make_write_dirty.\n\nTesting\n-------\n\n* Test on QEMU RISC-V, a virtio-net and an e1000e device was passed through\n to an L2 guest via vfio-pci + iommufd.\n\n* generic_pt KUnit: the existing test_dirty case now runs and passes for\n the RISC-V 64-bit format.\n\nFollow-up work\n--------------\n* Build a dedicated end-to-end test case that drives the full flow\n (HWPT_ALLOC with DIRTY_TRACKING -> attach -> IOAS_MAP -> generate real\n DMA -> SET_DIRTY_TRACKING -> GET_DIRTY_BITMAP -> verify bitmap against\n expected IOVA footprint) so that the behaviour can be regression-tested\n beyond the KUnit PTE-level coverage.\n\n* If possible, rebase and retest on top of the updated \"iommu irqbypass\"\n patchset.\n\n---\nChanges in v2 (Jason's suggestions):\n - Introduced a single PT_FEAT_RISCV_S2: second-stage selection is driven\n purely by this feature bit.\n - Switched from dynamic DC.tc.GADE toggling to static pre-enable.\n - domain_alloc_paging_flags: follow the switch/case design from other\n drivers.\n - Drop IOMMU_CAP_DEFERRED_FLUSH in riscv_iommu_capable.\n - Remove the .hw_info-related patch.\n - Link to v1:\n https://lore.kernel.org/linux-riscv/20260428131359.34872-1-fangyu.yu@linux.alibaba.com/\n\nFangyu Yu (6):\n iommupt: Add RISC-V Second-stage (iohgatp) page table support\n iommupt: Add RISC-V dirty tracking PTE ops\n iommu/riscv: Add domain_alloc_paging_flags for second-stage domain\n iommu/riscv: Pre-enable GADE for second-stage domains\n iommu/riscv: Add dirty tracking support for second-stage domains\n iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries\n\nTomasz Jeznach (2):\n iommu/riscv: report iommu capabilities\n RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch\n\nZong Li (2):\n iommu/riscv: use data structure instead of individual values\n iommu/riscv: support GSCID and GVMA invalidation command\n\n arch/riscv/kvm/Kconfig | 2 +\n drivers/iommu/generic_pt/fmt/riscv.h | 104 ++++++++++++++-\n drivers/iommu/riscv/iommu-bits.h | 7 +\n drivers/iommu/riscv/iommu.c | 190 +++++++++++++++++++++------\n include/linux/generic_pt/common.h | 5 +-\n include/linux/generic_pt/iommu.h | 17 ++-\n 6 files changed, 277 insertions(+), 48 deletions(-)"}