{"id":2233120,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2233120/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/20260505173029.2718246-1-terry.bowman@amd.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260505173029.2718246-1-terry.bowman@amd.com>","list_archive_url":null,"date":"2026-05-05T17:30:18","name":"[v17,00/11] Enable CXL PCIe Port Protocol Error handling and logging","submitter":{"id":82124,"url":"http://patchwork.ozlabs.org/api/1.2/people/82124/?format=json","name":"Bowman, Terry","email":"Terry.Bowman@amd.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/20260505173029.2718246-1-terry.bowman@amd.com/mbox/","series":[{"id":502875,"url":"http://patchwork.ozlabs.org/api/1.2/series/502875/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502875","date":"2026-05-05T17:30:19","name":"Enable CXL PCIe Port Protocol Error handling and logging","version":17,"mbox":"http://patchwork.ozlabs.org/series/502875/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2233120/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=pVQ5SR8U;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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helo=satlexmb07.amd.com; pr=C","From":"Terry Bowman ","To":", , ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ,\n\t, ,\n\t","CC":", ,\n\t, ,\n\t","Subject":"[PATCH v17 00/11] Enable CXL PCIe Port Protocol Error handling and\n logging","Date":"Tue, 5 May 2026 12:30:18 -0500","Message-ID":"<20260505173029.2718246-1-terry.bowman@amd.com>","X-Mailer":"git-send-email 2.34.1","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain","X-ClientProxiedBy":"satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"DM2PEPF00003FC2:EE_|BL3PR12MB6404:EE_","X-MS-Office365-Filtering-Correlation-Id":"fa5a9199-5dc2-4f03-d1e8-08deaacc05b5","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|56012099003|18002099003|921020;","X-Microsoft-Antispam-Message-Info":"\n\tW+Vc2lYOEr2t0/a/Szb/1K2ucUYgh3PerWbd1dW8A8nxpP0/fHBQPDNVvV14zO5q4p8JQz7JjmSAJhTnw339+XRmbNDph8aSvQHu1WEqmWzWv6NxaNagYGXFIkZxV6AvIN3+ujxiKHlx1JI8tDte6gcWgjnM2YB53KcromrSoTakAqahoWiNm4OOT/FdnnSzxM6rchbAED79BPwHvXZ3WhQvx1awxyB71L1KxteVo8vun1iU7aEruDrB6u8ZGI3H2M2nayyD1j76EOvUBjGj0EU2HiEV6hFTVY1BODyxd+TYILwghTV6yMNEgz8MVX8eSBdmfqNxLxI0I4OGrBBYrt7ixVDW3J1B55TDHGip988PjGLP/2dVAmpdkzxzETUkpL9lXZqMD5+0XPWuuoqRSOhSItXkVAGB5bg1XSaqf0D+1VU6bnWfgdTyUpdFHuug82TMgBV/WW3tnTtgwe4RMRSkRe1L/Nqynquzgy59mjs0YA2WbPAHRveKEg9AnZTheeC3t7WZloEcEbRw4+4dZIdMQWo5Kt+z1yTazLzXXPJDMsD1ZKlz8ZgMReRp+pfZUxcKNXobM88LbsMHHFWQjZ+ujU/t7YfMGqcyBRTBARaleOY34DZq3ElY7KaoOVZsaPo6pzQ2fCzYhqIxVeaWxudWMPoMJKfVatXu+C+tLB0VuX+YbpMqppyz3b5XEB7pNgEkkYGlnLUB/CC/A9DJ+sr4rAZ2iHjeyaNsJGlyo6Wrmbl2sX66pRqDH/F0PAAoNU7XExcJbU8nBEww+vbFa8s/X44iA3HH/eI0Z0PD7H0=","X-Forefront-Antispam-Report":"\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(82310400026)(1800799024)(56012099003)(18002099003)(921020);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tAEsTaW8Qp6joWli8WBkFfDVogMLxTxgast5ylv9cwj2C+ZzNes81M6FTe3jxazLF0gOsM2zuii7Vb4UtrZUrw23vYD6zKqnloxxhzE7tuuUxeVxwR88Qu0wd6kb7avCdUbZ2i3DcnjmV3+wjbtxgxQxqNNjLPQ2q8HVtwBM4K8uvQjR0RHUsZPK5mIENYqoHuf70C2px6P7w7dTkrTquhrYl4szSAVrJPV5yKj6zHQx2ZJgCYgzjhaVfDlLMS6VP0uo906Vxj8f7vfOBsRQaJYan0doYUVGBCrH1GLLeERY+CeZww7eQs0XS6ER/GXbc1YiLAEoEPL57selmc1ejX9osZkJ+SW20Tg4w25AOzZVbTd4utBTSHcCRIeMu4AR2obS66pKuo88KUvJNmjETrvoRk0+k0WLcpXznMcSq8bvMu41hDLGKea4mri53xO8m","X-OriginatorOrg":"amd.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"05 May 2026 17:30:37.8301\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n fa5a9199-5dc2-4f03-d1e8-08deaacc05b5","X-MS-Exchange-CrossTenant-Id":"3dd8961f-e488-4e60-8e11-a82d994e183d","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tDM2PEPF00003FC2.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BL3PR12MB6404"},"content":"This patch series enables CXL protocol error handling for both CXL Ports\nand CXL Endpoints (EP). The previous revision is available at:\n\nhttps://lore.kernel.org/linux-cxl/20260302203648.2886956-1-terry.bowman@amd.com/\n\nToday the kernel handles native CXL.cachemem RAS only for Endpoints and\nRestricted CXL Host (RCH) Downstream Ports. Root Ports, Upstream Switch\nPorts, and Downstream Switch Ports are uncovered. This series introduces\na unified CXL protocol error path for all CXL device types, in both VH\nand RCH topologies.\n\nCXL protocol errors are layered as a distinct error plane on top of PCIe\nAER. CXL RAS conditions are signaled as PCIe correctable (CE) and\nuncorrectable (UCE) Internal AER Errors. The AER driver classifies these\nevents using pcie_is_cxl() and hands them off to cxl_core through the\nAER-CXL kfifo.\n\nThe cxl_core driver dequeues each event, resolves the cxl_port topology,\nand dispatches to the CE or UCE handler. RCD Endpoints are handled\nslightly differently: the RCH Downstream Port's RAS state is processed\nfirst, then the Endpoint's own RAS follows the common path.\n\nPCIe AER errors remain a separate plane and are handled independently.\nThis series tightens the CXL Endpoint AER UCE handler and removes the\nEndpoint AER CE handler, which is now redundant since the AER driver\nclears and logs CE status itself.\n\nPCI_ERS_RESULT_PANIC, introduced in earlier revisions, has been dropped.\nThe panic decision is made directly in cxl_do_recovery(): the kernel\npanics on any uncorrectable CXL RAS error reported by cxl_handle_ras(),\nor earlier on link disconnect.\n\nA fatal UCE on an Upstream Switch Port or Endpoint surfaces through the\nAER path rather than the CXL RAS path. USP devices are bound to the PCIe\nportdrv driver, so when a USP reports a fatal UCE, the PCIe error\nhandler provided by portdrv is invoked. PCI config reads to the source\ndevice are expected to fail in this scenario, so the AER core never\nretrieves UNCOR_STATUS, and the event cannot be classified as CXL. See\nthe fatal and non-fatal log excerpts for USP and EP below.\n\nThe last patch is documentation with a diagram conveying the above.\n\n\n== Patch Details ==\n\nPatch 1 - PCI/AER: Introduce AER-CXL Kfifo\nAdds the AER-CXL kfifo in drivers/pci/pcie/aer_cxl_vh.c along with the\nproducer helper cxl_forward_error() and the consumer registration\nhelpers cxl_register_proto_err_work() and cxl_unregister_proto_err_work().\nThe kfifo is intended to deliver CXL VH protocol errors from the AER\ndriver to cxl_core. The producer dispatch in handle_error_source() and\nthe consumer registration are added together in patch 6 so the path\ngoes live atomically.\n\nPatch 2 - cxl/ras: Unify Endpoint and Port AER trace events\nUnifies the Endpoint and Port AER trace events into a single set used by\nall CXL devices on both the CPER and native AER paths. THIS IS AN ABI\nCHANGE FOR USERSPACE TOOLS THAT KEY OFF THE OLD ENDPOINT TRACE FIELD\nNAMES.\n\nPatch 3 - cxl: Use common CPER handling for all CXL devices\nFolds the Port and Endpoint paths in CPER protocol error handling into a\nsingle code path.\n\nPatch 4 - cxl: Rename find_cxl_port() to find_cxl_port_by_dport()\nRenames find_cxl_port() to find_cxl_port_by_dport() to make the lookup\nmethod explicit and consistent with the existing find_cxl_port_by_uport().\nBoth helpers remain static to core/port.c; patch 6 widens their scope\nwhen it adds the first cross-file caller.\n\nPatch 5 - cxl: Limit CXL-CPER kfifo registration functions scope\nLimits the scope of the CXL-CPER kfifo registration functions and adds\nwork cancellation on unregister.\n\nPatch 6 - PCI: Establish common CXL Port protocol error flow\nDequeues work from the AER-CXL kfifo and establishes a common flow for\nall CXL Port protocol error handling. It directs CXL protocol errors to\ncorrectable or uncorrectable handlers, and panics on any uncorrectable\nCXL RAS error.\n\nPatch 7 - PCI/CXL: Add RCH support to CXL handlers\nAdds CXL1.1 Restricted CXL Host (RCH) support to the new common flow.\nBehavior change: an RCD uncorrectable CXL RAS error now panics, matching\nthe policy applied to all other CXL devices. The RCH trace events also\nchange to report by PCI BDF instead of memdev name.\n\nPatch 8 - cxl: Remove Endpoint AER correctable handler\nRemoves the CXL PCIe AER correctable handler. The handling and logging is\nalready performed by the AER driver and the new common flow.\n\nPatch 9 - cxl: Update Endpoint AER uncorrectable handler\nReplaces cxl_error_detected() with cxl_pci_error_detected(). The new\nhandler decides solely on the pci_channel_state_t parameter and does not\naccess PCIe AER capability registers from .error_detected, matching the\npattern used by NVMe, ixgbe, mlx5, and other modern PCIe drivers.\nCXL.cachemem-corrupting protocol errors are routed separately through\nthe AER-CXL kfifo to cxl_handle_proto_error(), so cxl_pci does not need\nto second-guess the AER core's classification.\n\nPatch 10 - PCI/CXL: Mask/Unmask CXL protocol errors\nEnables CXL Internal Error reporting on CXL Ports and Endpoints. The\nunmask is paired with the RAS register block mapping in\ncxl_dport_map_ras() and devm_cxl_port_ras_setup() so it only runs when\nRAS registers were successfully mapped. The matching mask is registered\nas a devres action and runs when the cxl_port device's devres is\nreleased.\n\nPatch 11 - Documentation: cxl: Document CXL protocol error handling\nAdds Documentation/driver-api/cxl/linux/protocol-error-handling.rst\ndescribing the end-to-end CXL protocol error path: AER ingress, the\nAER-CXL kfifo handoff, the cxl_core consumer worker, RCD/RCH special\ncases, severity policy, trace events, and a source code map.\n\n== Notes ==\n\n- @Bjorn, I kindly request your review for the following patches. Many\n of the changes are to CXL-specific files in the PCI tree:\n\n Patch 1 - PCI/AER: Introduce AER-CXL Kfifo\n Patch 6 - PCI: Establish common CXL Port protocol error flow\n Patch 7 - PCI/CXL: Add RCH support to CXL handlers\n Patch 10 - PCI/CXL: Mask/Unmask CXL protocol errors\n\n- USP/EP fatal UCE follows the AER path because of how the AER core\n collects status. aer_get_device_error_info() only reads\n PCI_ERR_UNCOR_STATUS for Root Ports/RCECs/Downstream Ports or\n non-fatal severities, where config reads to the source are still\n expected to succeed. For a fatal UCE signaled by an upstream\n component, config reads to that device are expected to fail, so\n UNCOR_STATUS is never retrieved. Without the status word,\n is_cxl_error() cannot classify the event as CXL and the AER path\n handles it.\n\n- Dan's related series addressing RAS setup has more details:\n https://lore.kernel.org/linux-cxl/20260131000403.2135324-1-dan.j.williams@intel.com/\n\n- TODOs for future series:\n - Add Port support to CXL CLI injection (Ben)\n - Move aer_cxl_rch.c to cxl/core/ras_rch.c\n - Move RCH traversing for handling from AER driver into CXL driver\n - Investigate if cxl_pci UCE error handler can be removed.\n - Support user-defined status masks\n - Add CXL Port traversing in cxl_do_recovery()\n \n== Testing ==\n\nBelow are the testing results while using QEMU. The QEMU testing uses a CXL\nRoot Port, a CXL Upstream Switch Port, four CXL Downstream Switch Ports,\nand four CXL Type 3 Endpoints as given below. I've attached the QEMU\nstartup commandline used. This testing uses protocol error injection at one\nof each device class (Root Port, USP, DSP, Endpoint).\n\nThe test setup uses a modified aer-inject that supports CE and UCE\nInternal Error injection. Because the QEMU CXL devices do not provide a\nway to set the CXL RAS UNCOR_STATUS / COR_STATUS registers from\nuserspace, a separate out-of-tree debug patch (\"test/cxl: Force RAS\nstatus in cxl_handle_cor_ras() and cxl_handle_ras()\") is applied on top\nof the series for these tests, unconditionally OR'ing a Cache Data ECC\nbit into the RAS status read. That debug patch is intentionally NOT part\nof this v17 posting; reviewers reproducing the logs below in QEMU will\nneed it (or equivalent QEMU support) to see the CXL RAS trace events.\n\nThe sub-topology for the QEMU testing is:\n\n ---------------------\n | CXL RP - 0C:00.0 |\n ---------------------\n |\n ---------------------\n | CXL USP - 0D:00.0 |\n ---------------------\n |\n +-------------+---------+---------+-------------+\n | | | |\n ---------------- ---------------- ---------------- ----------------\n |CXL DSP | |CXL DSP | |CXL DSP | |CXL DSP |\n | 0E:00.0 | | 0E:01.0 | | 0E:02.0 | | 0E:03.0 |\n ---------------- ---------------- ---------------- ----------------\n | | | |\n ---------------- ---------------- ---------------- ----------------\n | CXL EP | | CXL EP | | CXL EP | | CXL EP |\n | 0F:00.0 | | 10:00.0 | | 11:00.0 | | 12:00.0 |\n ---------------- ---------------- ---------------- ----------------\n\n root@tbowman-cxl:~# lspci -t\n -+-[0000:00]-+-00.0\n | +-01.0\n | +-02.0\n | +-03.0\n | +-1f.0\n | +-1f.2\n | \\-1f.3\n \\-[0000:0c]---00.0-[0d-12]----00.0-[0e-12]--+-00.0-[0f]----00.0\n +-01.0-[10]----00.0\n +-02.0-[11]----00.0\n \\-03.0-[12]----00.0\n\n=== Root Port - CE ===\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00004000/00000000 into device 0000:0c:00.0\npcieport 0000:0c:00.0: AER: Correctable error message received from 0000:0c:00.0\naer_event: 0000:0c:00.0 CXL Bus Error: severity=Corrected, Corrected Internal Error, TLP Header=Not available\npcieport 0000:0c:00.0: CXL Bus Error: severity=Correctable, type=Transaction Layer, (Receiver ID)\npcieport 0000:0c:00.0: device [8086:7075] error status/mask=00004000/0000a000\npcieport 0000:0c:00.0: [14] CorrIntErr\ncxl_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'Cache Data ECC Error'\n\n== Root Port - UCE ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0c:00.0\npcieport 0000:0c:00.0: AER: Uncorrectable (Fatal) error message received from 0000:0c:00.0\naer_event: 0000:0c:00.0 CXL Bus Error: severity=Fatal, Uncorrectable Internal Error, TLP Header=Not available\npcieport 0000:0c:00.0: CXL Bus Error: severity=Uncorrectable (Fatal), type=Transaction Layer, (Receiver ID)\npcieport 0000:0c:00.0: device [8086:7075] error status/mask=00400000/02000000\npcieport 0000:0c:00.0: [22] UncorrIntErr\ncxl_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'Cache Data Parity Error' first_error: 'Cache Data Parity Error'\nKernel panic - not syncing: CXL cachemem error.\nCPU: 7 UID: 0 PID: 199 Comm: kworker/7:1 Not tainted 7.1.0-rc2-00011-g8cbf75633e69 #26 PREEMPT(lazy)\nHardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.16.3-0-ga6ed6b701f0a-prebuilt.qemu.org 04/01/2014\nWorkqueue: events cxl_proto_err_work_fn [cxl_core]\nCall Trace:\n \n vpanic+0x453/0x4b0\n panic+0x56/0x60\n __cxl_proto_err_work_fn+0x265/0x280 [cxl_core]\n ? __pfx___cxl_proto_err_work_fn+0x10/0x10 [cxl_core]\n for_each_cxl_proto_err+0x50/0x90\n cxl_proto_err_work_fn+0x27/0x80 [cxl_core]\n process_one_work+0x16e/0x3c0\n worker_thread+0x172/0x2e0\n ? __pfx_worker_thread+0x10/0x10\n kthread+0xe5/0x120\n ? __pfx_kthread+0x10/0x10\n ret_from_fork+0x1bd/0x220\n ? __pfx_kthread+0x10/0x10\n ret_from_fork_asm+0x1a/0x30\n \nKernel Offset: disabled\n---[ end Kernel panic - not syncing: CXL cachemem error. ]---\n\n== Upstream Switch Port - CE ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00004000/00000000 into device 0000:0d:00.0\npcieport 0000:0c:00.0: AER: Correctable error message received from 0000:0d:00.0\naer_event: 0000:0d:00.0 CXL Bus Error: severity=Corrected, Corrected Internal Error, TLP Header=Not available\npcieport 0000:0d:00.0: CXL Bus Error: severity=Correctable, type=Transaction Layer, (Receiver ID)\npcieport 0000:0d:00.0: device [19e5:a128] error status/mask=00004000/0000a000\npcieport 0000:0d:00.0: [14] CorrIntErr\ncxl_aer_correctable_error: device=0000:0d:00.0 host=0000:0c:00.0 serial=0 status: 'Cache Data ECC Error'\n\n== Upstream Switch Port - UCE (fatal - AER recovery) ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0d:00.0\npcieport 0000:0c:00.0: AER: Uncorrectable (Fatal) error message received from 0000:0d:00.0\naer_event: 0000:0d:00.0 CXL Bus Error: severity=Fatal, , TLP Header=Not available\npcieport 0000:0d:00.0: AER: CXL Bus Error: severity=Uncorrectable (Fatal), type=Inaccessible, (Unregistered Agent ID)\ncxl_pci 0000:0f:00.0: mem1: frozen state error detected, disable CXL.mem\ncxl_pci 0000:10:00.0: mem0: frozen state error detected, disable CXL.mem\ncxl_pci 0000:11:00.0: mem3: frozen state error detected, disable CXL.mem\ncxl_pci 0000:12:00.0: mem2: frozen state error detected, disable CXL.mem\npcieport 0000:0c:00.0: AER: Root Port link has been reset (0)\ncxl_pci 0000:0f:00.0: mem1: restart CXL.mem after slot reset\ncxl_pci 0000:10:00.0: mem0: restart CXL.mem after slot reset\ncxl_pci 0000:11:00.0: mem3: restart CXL.mem after slot reset\ncxl_pci 0000:12:00.0: mem2: restart CXL.mem after slot reset\ncxl_pci 0000:0f:00.0: mem1: error resume successful\ncxl_pci 0000:10:00.0: mem0: error resume successful\ncxl_pci 0000:11:00.0: mem3: error resume successful\ncxl_pci 0000:12:00.0: mem2: error resume successful\npcieport 0000:0c:00.0: AER: device recovery successful\n\n== Upstream Switch Port - UCE (non-fatal - panic) ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0d:00.0\npcieport 0000:0c:00.0: AER: Uncorrectable (Non-Fatal) error message received from 0000:0d:00.0\naer_event: 0000:0d:00.0 CXL Bus Error: severity=Uncorrected, non-fatal, Uncorrectable Internal Error, TLP Header=Not available\npcieport 0000:0d:00.0: CXL Bus Error: severity=Uncorrectable (Non-Fatal), type=Transaction Layer, (Receiver ID)\npcieport 0000:0d:00.0: device [19e5:a128] error status/mask=00400000/02000000\npcieport 0000:0d:00.0: [22] UncorrIntErr\ncxl_aer_uncorrectable_error: device=0000:0d:00.0 host=0000:0c:00.0 serial=0 status: 'Cache Data Parity Error' first_error: 'Cache Data Parity Error'\nKernel panic - not syncing: CXL cachemem error.\nCPU: 7 UID: 0 PID: 54 Comm: kworker/7:0 Not tainted 7.1.0-rc2-00011-g8cbf75633e69 #26 PREEMPT(lazy)\nHardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.16.3-0-ga6ed6b701f0a-prebuilt.qemu.org 04/01/2014\nWorkqueue: events cxl_proto_err_work_fn [cxl_core]\nCall Trace:\n \n vpanic+0x453/0x4b0\n panic+0x56/0x60\n __cxl_proto_err_work_fn+0x265/0x280 [cxl_core]\n ? __pfx___cxl_proto_err_work_fn+0x10/0x10 [cxl_core]\n for_each_cxl_proto_err+0x50/0x90\n cxl_proto_err_work_fn+0x27/0x80 [cxl_core]\n process_one_work+0x16e/0x3c0\n worker_thread+0x172/0x2e0\n ? __pfx_worker_thread+0x10/0x10\n kthread+0xe5/0x120\n ? __pfx_kthread+0x10/0x10\n ret_from_fork+0x1bd/0x220\n ? __pfx_kthread+0x10/0x10\n ret_from_fork_asm+0x1a/0x30\n \nKernel Offset: disabled\n---[ end Kernel panic - not syncing: CXL cachemem error. ]---\n\n== Downstream Switch Port - CE ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00004000/00000000 into device 0000:0e:00.0\npcieport 0000:0c:00.0: AER: Correctable error message received from 0000:0e:00.0\naer_event: 0000:0e:00.0 CXL Bus Error: severity=Corrected, Corrected Internal Error, TLP Header=Not available\npcieport 0000:0e:00.0: CXL Bus Error: severity=Correctable, type=Transaction Layer, (Receiver ID)\npcieport 0000:0e:00.0: device [19e5:a129] error status/mask=00004000/0000a000\npcieport 0000:0e:00.0: [14] CorrIntErr\ncxl_aer_correctable_error: device=0000:0e:00.0 host=0000:0d:00.0 serial=0 status: 'Cache Data ECC Error'\n\n== Downstream Switch Port - UCE (fatal) ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0e:00.0\npcieport 0000:0c:00.0: AER: Uncorrectable (Fatal) error message received from 0000:0e:00.0\naer_event: 0000:0e:00.0 CXL Bus Error: severity=Fatal, Uncorrectable Internal Error, TLP Header=Not available\npcieport 0000:0e:00.0: CXL Bus Error: severity=Uncorrectable (Fatal), type=Transaction Layer, (Receiver ID)\npcieport 0000:0e:00.0: device [19e5:a129] error status/mask=00400000/02000000\npcieport 0000:0e:00.0: [22] UncorrIntErr\ncxl_aer_uncorrectable_error: device=0000:0e:00.0 host=0000:0d:00.0 serial=0 status: 'Cache Data Parity Error' first_error: 'Cache Data Parity Error'\nKernel panic - not syncing: CXL cachemem error.\nCPU: 7 UID: 0 PID: 211 Comm: kworker/7:1 Not tainted 7.1.0-rc2-00011-g8cbf75633e69 #26 PREEMPT(lazy)\nHardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.16.3-0-ga6ed6b701f0a-prebuilt.qemu.org 04/01/2014\nWorkqueue: events cxl_proto_err_work_fn [cxl_core]\nCall Trace:\n \n vpanic+0x453/0x4b0\n panic+0x56/0x60\n __cxl_proto_err_work_fn+0x265/0x280 [cxl_core]\n ? __pfx___cxl_proto_err_work_fn+0x10/0x10 [cxl_core]\n for_each_cxl_proto_err+0x50/0x90\n cxl_proto_err_work_fn+0x27/0x80 [cxl_core]\n process_one_work+0x16e/0x3c0\n worker_thread+0x172/0x2e0\n ? __pfx_worker_thread+0x10/0x10\n kthread+0xe5/0x120\n ? __pfx_kthread+0x10/0x10\n ret_from_fork+0x1bd/0x220\n ? __pfx_kthread+0x10/0x10\n ret_from_fork_asm+0x1a/0x30\n \nKernel Offset: disabled\n---[ end Kernel panic - not syncing: CXL cachemem error. ]---\n\n== Endpoint - CE ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00004000/00000000 into device 0000:0f:00.0\npcieport 0000:0c:00.0: AER: Correctable error message received from 0000:0f:00.0\naer_event: 0000:0f:00.0 CXL Bus Error: severity=Corrected, Corrected Internal Error, TLP Header=Not available\ncxl_pci 0000:0f:00.0: CXL Bus Error: severity=Correctable, type=Transaction Layer, (Receiver ID)\ncxl_pci 0000:0f:00.0: device [8086:0d93] error status/mask=00004000/0000a000\ncxl_pci 0000:0f:00.0: [14] CorrIntErr\ncxl_aer_correctable_error: device=0000:0f:00.0 host=0000:0e:00.0 serial=0 status: 'Cache Data ECC Error'\n\n== Endpoint - UCE (fatal - AER recovery) ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0f:00.0\npcieport 0000:0c:00.0: AER: Uncorrectable (Fatal) error message received from 0000:0f:00.0\naer_event: 0000:0f:00.0 CXL Bus Error: severity=Fatal, , TLP Header=Not available\ncxl_pci 0000:0f:00.0: AER: CXL Bus Error: severity=Uncorrectable (Fatal), type=Inaccessible, (Unregistered Agent ID)\ncxl_pci 0000:0f:00.0: mem0: frozen state error detected, disable CXL.mem\npcieport 0000:0e:00.0: AER: Downstream Port link has been reset (0)\ncxl_pci 0000:0f:00.0: mem0: restart CXL.mem after slot reset\ncxl_pci 0000:0f:00.0: mem0: error resume successful\npcieport 0000:0e:00.0: AER: device recovery successful\n\n== Endpoint - UCE (non-fatal) ==\n\npcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0f:00.0\npcieport 0000:0c:00.0: AER: Uncorrectable (Non-Fatal) error message received from 0000:0f:00.0\naer_event: 0000:0f:00.0 CXL Bus Error: severity=Uncorrected, non-fatal, Uncorrectable Internal Error, TLP Header=Not available\ncxl_pci 0000:0f:00.0: CXL Bus Error: severity=Uncorrectable (Non-Fatal), type=Transaction Layer, (Receiver ID)\ncxl_pci 0000:0f:00.0: device [8086:0d93] error status/mask=00400000/02000000\ncxl_pci 0000:0f:00.0: [22] UncorrIntErr\ncxl_aer_uncorrectable_error: device=0000:0f:00.0 host=0000:0e:00.0 serial=0 status: 'Cache Data Parity Error' first_error: 'Cache Data Parity Error'\nKernel panic - not syncing: CXL cachemem error.\nCPU: 7 UID: 0 PID: 201 Comm: kworker/7:1 Not tainted 7.1.0-rc2-00011-g8cbf75633e69 #26 PREEMPT(lazy)\nHardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.16.3-0-ga6ed6b701f0a-prebuilt.qemu.org 04/01/2014\nWorkqueue: events cxl_proto_err_work_fn [cxl_core]\nCall Trace:\n \n vpanic+0x453/0x4b0\n panic+0x56/0x60\n __cxl_proto_err_work_fn+0x265/0x280 [cxl_core]\n ? __pfx___cxl_proto_err_work_fn+0x10/0x10 [cxl_core]\n for_each_cxl_proto_err+0x50/0x90\n cxl_proto_err_work_fn+0x27/0x80 [cxl_core]\n process_one_work+0x16e/0x3c0\n worker_thread+0x172/0x2e0\n ? __pfx_worker_thread+0x10/0x10\n kthread+0xe5/0x120\n ? __pfx_kthread+0x10/0x10\n ret_from_fork+0x1bd/0x220\n ? __pfx_kthread+0x10/0x10\n ret_from_fork_asm+0x1a/0x30\n \nKernel Offset: disabled\n---[ end Kernel panic - not syncing: CXL cachemem error. ]---\n\n== Changes ==\n\nChanges in v16->v17:\nPCI/AER: Introduce AER-CXL Kfifo\n- Reword \"kfifo semaphore\" to \"kfifo spinlock\" to match fifo_lock.\n- Defer the handle_error_source() is_cxl_error() switch to the patch that\n registers the kfifo consumer to keep each commit bisect-safe.\n- Rename rwsema to rwsem\n- Change CPER exports to use EXPORT_SYMBOL_FOR_MODULES.\n- Add work cancel function.\n- Replace kfifo_put() with kfifo_in_spinlocked() for multiple producers\n- Add fifo_lock spinlock for concurrent producer serialisation\n- Initialize the embedded kfifo with INIT_KFIFO() in a subsys_initcall so\n kfifo->mask, ->esize and ->data are set before first use.\n- Clear PCI_ERR_COR_STATUS in cxl_forward_error() before enqueue so the\n device is acked for correctable events even when the consumer drops the\n event. Uncorrectable status is left for cxl_do_recovery() to clear after\n recovery completes, mirroring the AER core convention.\n- WARN on double-registration in cxl_register_proto_err_work() to make an\n unintended second consumer visible at runtime.\n- Add direct rwsem.h, cleanup.h and workqueue.h includes for symbols used\n in aer_cxl_vh.c\n- Add MAINTAINERS entries for drivers/pci/pcie/aer_cxl_*.c\n- Update message\ncxl/ras: Unify Endpoint and Port AER trace events\n- Replace cxlds->serial with pci_get_dsn()\n- Change 'memdev' to 'device' (Dan)\n- Updated Commit message\ncxl: Use common CPER handling for all CXL devices\n- New commit\ncxl: Rename find_cxl_port() to find_cxl_port_by_dport()\n- New commit\n- Drop the de-staticisation of find_cxl_port_by_uport() and the\n core.h declarations from this prep patch; both move to the patch\n that introduces the first cross-file caller.\ncxl: Limit CXL-CPER kfifo registration functions scope\n- Split from v16 02/10 (\"Update unregistration for AER-CXL and\n CPER-CXL kfifos\"); AER-CXL half folded into v17 01/10.\n- Convert exports to EXPORT_SYMBOL_FOR_MODULES(\"cxl_core\").\n- Change register/unregister return type from int to void.\n- Drop work_struct argument from cxl_cper_unregister_prot_err_work();\n it now cancels its own work.\n- Remove now-redundant cancel_work_sync() from cxl_ras_exit().\n- Add WARN_ONCE() in cxl_cper_register_prot_err_work() for\n double-registration.\nPCI: Establish common CXL Port protocol error flow\n- get_cxl_port() -> find_cxl_port_by_dev()\n- Simplified find_cxl_port_by_dev()\n- Replace and remove cxl_serial_number() w/ pci_get_dsn()\n- cxl_get_ras_base() -> to_ras_base()\n- Drop dependency on PCI_ERS_RESULT_PANIC; cxl_do_recovery() panics\n directly. (PANIC enum patch dropped from series.)\n- Clarify panic semantics: panic on any uncorrectable CXL RAS error, not\n only AER-FATAL severities.\n- Drop the redundant PCI_ERR_COR_STATUS RMW in cxl_handle_proto_error();\n cxl_forward_error() already acks the correctable AER status.\n- Add is_cxl_error() switch in handle_error_source() here, paired with the\n kfifo consumer registration, to keep each commit bisect-safe.\n- Drop pcie_aer_is_native() guard in cxl_do_recovery() (always native).\n- Swap order with the \"Limit\" patch for bisectability w/ cxl_ras_exit()\n- Reword for \"any uncorrectable\" CXL RAS error panics.\n- Restore log messages for port-not-found and port-unbound cases.\n- Whitespace cleanup (Jonathan)\n- Update to get_cxl_port() documentation (Terry)\n- Fix __cxl_proto_err_work_fn() to return 0 for transient errors.\n- Drop !port check in cxl_do_recovery(), caller already validated\n- Fix kerneldoc @pdev -> @dev in find_cxl_port_by_dev()\n- Fix missing space in pr_err_ratelimited()\n- Add disconnect check before access\n- Made pcie_clear_device_status() and pci_aer_clear_fatal_status()\n EXPORT_SYMBOL_FOR_MODULES(\"cxl_core\") (Dan)\n- Move find_cxl_port_by_dport() and find_cxl_port_by_uport()\n de-staticisation and core.h declarations from the rename patch to\n here, where the first cross-file callers in find_cxl_port_by_dev()\n land.\nPCI/CXL: Add RCH support to CXL handlers\n- Drop now-dead cxlds->rcd branches from cxl_{cor_,}error_detected().\n- Drop duplicate subject line from commit body.\n- Document panic-on-uncorrectable behavior change for RCD path.\n- Document trace event device-name change (memN -> PCI BDF) for RCH path.\n- Rewrite cxl_handle_proto_error() RC_END comment to clarify RCD/RCH shared\n interrupt relationship\n- Rewrite commit message\ncxl: Remove Endpoint AER correctable handler\n- Update commit message\n- Add Reviewed-by from Jonathan and DaveJ\ncxl: Update Endpoint AER uncorrectable handler\n- Rename pci_error_handlers struct instance to cxl_pci_error_handlers to\n avoid shadowing the struct type tag.\n- Restore scoped_guard(device) and dev->driver check around AER read.\n- NULL-check find_cxl_port_by_dev() before deref of port->uport_dev.\n- Updated commit message. (Terry)\n- Add scope cleanup for port variable in cxl_pci_error_detected() (Terry)\n- Drop cxl_uncor_aer_present(), rely on AER state\nPCI/CXL: Mask/Unmask CXL protocol errors\n- Drop redundant cxl_mask_proto_interrupts() calls from unregister_port()\n and cxl_dport_remove(); the devres action registered alongside the unmask\n is the sole mask path.\n- Update title\n- Remove unnecessary check for aer_capabilities\n- Gate cxl_unmask_proto_interrupts() on pcie_aer_is_native()\n- Add pci_aer_mask_internal_errors() and cxl_mask_proto_interrupts()\n- Only unmask on successful cxl_map_component_regs()\n- NULL-check @dev in cxl_{un,}mask_proto_interrupts()\n- Drop static and declare in core/core.h\nDocumentation: cxl: Document CXL protocol error handling\n- New commit\n\nChanges in v15->v16:\nPCI/AER: Introduce AER-CXL Kfifo\n- Add pci_dev_put() and comment at pci_dev_get() (Dan)\n- /rw_sema/rwsema/ (Dan)\n- Split validation checks in cxl_forward_error() to allow\n for meaningful reason in log (Terry)\n- Shortened commit title to remove wordiness (Terry)\nPCI/CXL: Update unregistration for AER-CXL and CPER-CXL kfifos\n- New commit\ncxl: Update CXL Endpoint tracing\n- Add Dan's review-by\n- Incorporate Dan's comment into commit message:\n \"Add the serial number at the end to preserve compatibility with\n libtraceevent parsing of the parameters.\"\nPCI/ERR: Introduce PCI_ERS_RESULT_PANIC\n- None\nPCI: Establish common CXL Port protocol error flow\n- get_ras_base(), initialize dport to NULL (Jonathan)\n- Remove guard(device)(&cxlmd->dev) (Jonathan)\n- Fix dev_warns() (Jonathan)\n- Remove comment in cxl_port_error_detected() (Dan)\n- Made pcie_clear_device_status() and pci_aer_clear_fatal_status()\n \"CXL\" Export namespace (Dan)\n- Update switch-case brackets to follow clang-format (Dan)\n- Add PCI_EXP_TYPE_RC_END for cxl_get_ras_base() (Terry)\n- Add NULL port check in cxl_serial_number() (Terry)\nPCI/CXL: Add RCH support to CXL handlers\n- New commit\ncxl: Update error handlers to support CXL Port devices\n- None\ncxl: Update Endpoint AER uncorrectable handler\n- Update commit message (DaveJ)\n- s/cxl_handle_aer()/cxl_uncor_aer_present()/g (Jonathan)\n- cxl_uncor_aer_present(): Leave original result calculation based on\n if a UCE is present and the provided state (Terry)\n- Add call to pci_print_aer(). AER fails to log because is upstream\n link (Terry)\ncxl: Remove Endpoint AER correctable handler\n- None\ncxl: Enable CXL protocol error reporting\n- None\n\nChanges in v14->v15:\n PCI/AER: Introduce AER-CXL Kfifo in new file, pcie/aer_cxl_vh.c\n - Move pci_dev_get() call to this patch (Dave)\n cxl: Update CXL Endpoint tracing\n - Update commit message\n - Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (Terry)\n PCI/ERR: Introduce PCI_ERS_RESULT_PANIC\n - None\n PCI/AER: Dequeue forwarded CXL error\n - Move pci_dev_get() to cxl_forward_error() (Dave)\n - Move in is_cxl_error() change from later patch (Terry)\n PCI: Establish common CXL Port protocol error flow\n - Update commit message and title. Added Bjorn's ack.\n - Move CE and UCE handling logic here (Terry)\n cxl: Update error handlers to support CXL Port protocol errors\n - New commit (Terry)\n cxl: Update Endpoint AER uncorrectable handler\n - Title update (Terry)\n - Change cxl_pci_error-detected() to handle & log AER (Terry)\n - Update commit message (Terry)\n - Moved cxl_handle_ras()/cxl_handle_cor_ras() to earlier patch (Terry)\n cxl: Remove Endpoint AER correctable handler\n - Remove cxl_pci_cor_error_detected(). Is not needed. AER is logged\n in the AER driver. (Dan)\n - Update commit message (Terry)\n cxl: Enable CXL protocol error reporting\n - Update commit title's prefix (Bjorn)\n\nChanges in v13->v14:\n PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h\n - Add Jonathan's and Dan's review-by\n - Update commit title prefix (Bjorn)\n - Revert format fix for cxl_sbr_masked() (Jonathan)\n - Update 'Compute Express Link' comment block (Jonathan)\n - Move PCI_DVSEC_CXL_FLEXBUS definitions to later patch where\n used (Jonathan)\n - Removed stray change (Bjorn)\n PCI: Update CXL DVSEC definitions\n - New patch. Split from previous patch such that there is now a separate\n move patch and a format fix patch.\n - Formatting update requested (Bjorn)\n - Remove PCI_DVSEC_HEADER1_LENGTH_MASK because it duplicates\n PCI_DVSEC_HEADER1_LEN() (Bjorn)\n - Add Dan's review-by\n PCI: Introduce pcie_is_cxl()\n - Move FLEXBUS_STATUS DVSEC here (Jonathan)\n - Remove check for EP and USP (Dan)\n - Update commit message (Bjorn)\n - Fix writing past 80 columns (Bjorn)\n - Add pci_is_pcie() parent bridge check at beginning of function (Bjorn)\n PCI: Replace cxl_error_is_native() with pcie_aer_is_native()\n - New commit\n cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c\n - Add sign-off for Dan and Jonathan\n - Revert inadvertent formatting of cxl_dport_map_rch_aer() (Jonathan)\n - Remove default value for CXL_RCH_RAS (Dan)\n - Remove unnecessary pci.h include in core.h & ras_rch.c (Jonathan)\n - Add linux/types.h include in ras_rch.c (Jonathan)\n - Change CONFIG_CXL_RCH_RAS -> CONFIG_CXL_RAS (Dan)\n PCI/AER: Export pci_aer_unmask_internal_errors\n - New commit. Bjorn requested separating out and adding immediatetly\n before being used. This is called from cxl_rch_enable_rcec() in\n following patch.\n PCI/AER: Update is_internal_error() to be non-static is_aer_internal_error()\n - New commit\n PCI/AER: Move CXL RCH error handling to aer_cxl_rch.c\n - Add review-by and signed-off for Dan\n - Commit message fixup (Dan)\n - Update commit message with use-case description (Dan, Lukas)\n - Make cxl_error_is_native() static (Dan)\n - Make is_internal_error() non-static, non-export (Terry)\n PCI/AER: Use guard() in cxl_rch_handle_error_iter()\n - Add review-by for Jonathan, Dave Jiang, Dan WIlliams, and Bjorn\n - Remove cleanup.h (Jonathan)\n - Reverted comment removal (Bjorn)\n - Move this patch after pci/pcie/aer_cxl_rch.c creation (Bjorn)\n PCI/AER: Replace PCIEAER_CXL symbol with CXL_RAS\n - New commit\n PCI/AER: Report CXL or PCIe bus type in AER trace logging\n - Merged with Dan's commit. Changes are moving bus_type the last\n parameter in function calls (Dan)\n - Removed all DCOs because of changes (Terry)\n - Update commit message (Bjorn)\n - Add Bjorn's ack-by\n PCI/AER: Update struct aer_err_info with kernel-doc formatting\n - New commit\n cxl/mem: Clarify @host for devm_cxl_add_nvdimm()\n - New commit\n cxl/port: Remove \"enumerate dports\" helpers\n - New commit\n cxl/port: Fix devm resource leaks around with dport management\n - New commit\n cxl/port: Move dport operations to a driver event\n - New commit\n cxl/port: Move dport RAS reporting to a port resource\n - New commit\n cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers\n - Correct message spelling (Terry)\n cxl/port: Move endpoint component register management to cxl_port\n - Correct message spelling (Terry)\n cxl/port: Map Port component registers before switchport init\n - Updates to use cxl_port_setup_regs() (Dan)\n cxl: Change CXL handlers to use guard() instead of scoped_guard()\n - Add reviewed-by for Jonathan and Dave Jiang\n PCI/ERR: Introduce PCI_ERS_RESULT_PANIC\n - Add review-by for Dan\n - Update Title prefix (Bjorn)\n - Removed merge_result. Only logging error for device reporting the\n error (Dan)\n - Remove PCI_ERS_RESULT_PANIC paragraph in pci-error-recovery.rst (Bjorn)\n PCI/AER: Move AER driver's CXL VH handling to pcie/aer_cxl_vh.c\n - Replaced workqueue_types.h include with 'struct work_struct'\n predeclaration (Bjorn)\n - Update error message (Bjorn)\n - Reordered 'struct cxl_proto_err_work_data' (Bjorn)\n - Remove export of cxl_error_is_native() here (Bjorn)\n cxl/port: Unify endpoint and switch port lookup\n - New patch\n PCI/AER: Dequeue forwarded CXL error\n - Update commit title's prefix (Bjorn)\n - Add pdev ref get in AER driver before enqueue and add pdev ref put in\n CXL driver after dequeue and handling (Dan)\n - Removed handling to simplify patch context (Terry)\n PCI: Introduce CXL Port protocol error handlers\n - Add Dave Jiang's review-by\n - Update commit message & headline (Bjorn)\n - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to\n one line (Jonathan)\n - Remove cxl_walk_port(). Only log the erroring device. No port walking. (Dan)\n - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is\n sufficient (Dan)\n - Remove device_lock_if()\n - Combine CE and UCE here (Terry)\n cxl: Update Endpoint uncorrectable protocol error handling\n - Update commit headline (Bjorn)\n - Rename pci_error_detected()/pci_cor_error_detected() ->\n cxl_pci_error_detected/cxl_pci_cor_error_detected() (Jonathan)\n - Remove now-invalid comment in cxl_error_detected() (Jonathan)\n - Split into separate patches for UCE and CE (Terry)\n cxl: Update Endpoint correctable protocol error handling\n - New commit\n - Change cxl_cor_error_detected() parameter to &pdev->dev device from\n memdev device. (Terry)\n cxl: Enable CXL protocol errors during CXL Port probe\n - Update commit title's prefix (Bjorn)\n Changes in v12->v13:\n CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h\n - Add Dave Jiang's reviewed-by\n - Remove changes to existing PCI_DVSEC_CXL_PORT* defines. Update commit\n message. (Jonathan)\n PCI/CXL: Introduce pcie_is_cxl()\n - Add Ben's \"reviewed-by\"\n cxl/pci: Remove unnecessary CXL Endpoint handling helper functions\n - None\n cxl/pci: Remove unnecessary CXL RCH handling helper functions\n - None\n cxl: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core\n - None\n cxl: Move CXL driver's RCH error handling into core/ras_rch.c\n - None\n CXL/AER: Replace device_lock() in cxl_rch_handle_error_iter() with guard() lock\n - New patch\n CXL/AER: Move AER drivers RCH error handling into pcie/aer_cxl_rch.c\n - Add forward declararation of 'struct aer_err_info' in pci/pci.h (Terry)\n - Changed copyright date from 2025 to 2023 (Jonathan)\n - Add David Jiang's, Jonathan's, and Ben's review-by\n - Readd 'struct aer_err_info' (Bot)\n PCI/AER: Report CXL or PCIe bus error type in trace logging\n - Remove duplicated aer_err_info inline comments. Is already in the\n kernel-doc header (Ben)\n cxl/pci: Update RAS handler interfaces to also support CXL Ports\n - None\n cxl/pci: Log message if RAS registers are unmapped\n - Added Bens review-by\n cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports\n - Added Dave Jiang's review-by\n cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors\n - Add Ben's review-by\n cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers\n - Change as result of dport delay fix. No longer need switchport and\n endport approach. Refactor. (Terry)\n CXL/PCI: Introduce PCI_ERS_RESULT_PANIC\n - Add Dave Jiang's, Jonathan's, Ben's review-by\n - Typo fix (Ben)\n CXL/AER: Introduce pcie/aer_cxl_vh.c in AER driver for forwarding CXL errors\n - Add Dave Jiang's review-by\n - Update error message (Ben)\n cxl: Introduce cxl_pci_drv_bound() to check for bound driver\n - Add Dave Jiang's review-by.\n cxl: Change CXL handlers to use guard() instead of scoped_guard()\n - New patch\ncxl/pci: Introduce CXL protocol error handlers for endpoints\n - Updated all the implemetnation and commit message. (Terry)\n - Refactored cxl_cor_error_detected()/cxl_error_detected() to remove\n pdev (Dave Jiang)\nCXL/PCI: Introduce CXL Port protocol error handlers\n - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue\n patch (Terry)\n - Remove EP case in cxl_get_ras_base(), not used. (Terry)\n - Remove check for dport->dport_dev (Dave)\n - Remove whitespace (Terry)\nPCI/AER: Dequeue forwarded CXL error\n - Rewrite cxl_handle_proto_error() and cxl_proto_err_work_fn() (Terry)\n - Rename get_cxl_host dev() to be get_cxl_port() (Terry)\n - Remove exporting of unused function, pci_aer_clear_fatal_status() (Dave Jiang)\n - Change pr_err() calls to ratelimited. (Terry)\n - Update commit message. (Terry)\n - Remove namespace qualifier from pcie_clear_device_status()\n export (Dave Jiang)\n - Move locks into cxl_proto_err_work_fn() (Dave)\n - Update log messages in cxl_forward_error() (Ben)\nCXL/PCI: Export and rename merge_result() to pci_ers_merge_result()\n - Renamed pci_ers_merge_result() to pcie_ers_merge_result().\n pci_ers_merge_result() is already used in eeh driver. (Bot)\nCXL/PCI: Introduce CXL uncorrectable protocol error recovery\n - Rewrite report_error_detected() and cxl_walk_port (Terry)\n - Add guard() before calling cxl_pci_drv_bound() (Dave Jiang)\n - Add guard() calls for EP (cxlds->cxlmd->dev & pdev->dev) and ports\n (pdev->dev & parent cxl_port) in cxl_report_error_detected() and\n cxl_handle_proto_error() (Terry)\n - Remove unnecessary check for endpoint port. (Dave Jiang)\n - Remove check for RCIEP EP in cxl_report_error_detected() (Terry)\nCXL/PCI: Enable CXL protocol errors during CXL Port probe\n - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Terry)\n - Add Dave Jiang's and Ben's review-by\nCXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup\n - Added dev and dev_is_pci() checks in cxl_mask_proto_interrupts() (Terry)\n\nChanges in v11 -> v12:\n cxl/pci: Remove unnecessary CXL Endpoint handling helper functions\n - Added Dave Jiang's review by\n - Moved to front of series\n cxl/pci: Remove unnecessary CXL RCH handling helper functions\n - Add reviewed-by for Alejandro & Dave Jiang\n - Moved to front of series\n cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c\n - Update CONFIG_CXL_RAS in CXL Kconfig to have CXL_PCI dependency (Terry)\n CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS\n - Added review-by for Sathyanarayanan\n - Changed Kconfig dependency from PCIEAER_CXL to PCIEAER. Moved\n this backwards into this patch.\n cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditio\n - Moved CXL_RCH_RAS Kconfig definition here from following commit\n CXL/AER: Introduce aer_cxl_rch.c into AER driver for handling CXL RCH errors\n - Rename drivers/pci/pcie/cxl_rch.c to drivers/pci/pcie/aer_cxl_rch.c (Lukas)\n - Removed forward declararation of 'struct aer_err_info' in pci/pci.h (Terry)\n CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h\n - Change formatting to be same as existing definitions\n - Change GENMASK() -> __GENMASK() and BIT() to _BITUL()\n PCI/CXL: Introduce pcie_is_cxl()\n - Add review-by for Alejandro\n - Add comment in set_pcie_cxl() explaining why updating parent status.\n PCI/AER: Report CXL or PCIe bus error type in trace logging\n - Change aer_err_info::is_cxl to be bool a bitfield. Update structure padding. (Lukas)\n - Add kernel-doc for 'struct aer_err_info' (Lukas)\n cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports\n - Correct parameters to call trace_cxl_aer_correctable_error() (Shiju)\n - Add reviewed-by for Jonathan and Shiju\n cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers\n - Add check for dport_parent->rch before calling cxl_dport_init_ras_reporting().\n - RCH dports are initialized from cxl_dport_init_ras_reporting cxl_mem_probe().\n CXL/PCI: Introduce PCI_ERS_RESULT_PANIC\n - Documentation requested by (Lukas)\n CXL/AER: Introduce aer_cxl_vh.c in AER driver for forwarding CXL errors\n - Rename drivers/pci/pcie/cxl_aer.c to drivers/pci/pcie/aer_cxl_vh.c (Lukas)\n cxl: Introduce cxl_pci_drv_bound() to check for bound driver\n - New patch\n PCI/AER: Dequeue forwarded CXL error\n - Add guard for CE case in cxl_handle_proto_error() (Dave)\n - Updated commit message (Terry)\n CXL/PCI: Introduce CXL Port protocol error handlers\n - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and\n pci_to_cxl_dev() (Lukas)\n - Change cxl_error_detected() -> cxl_cor_error_detected() (Terry)\n - Remove NULL variable assignments (Jonathan)\n - Replace bus_find_device() with find_cxl_port_by_uport() for upstream\n port searches. (Dave)\n CXL/PCI: Export and rename merge_result() to pci_ers_merge_result()\n - Remove static inline pci_ers_merge_result() definition for !CONFIG_PCIEAER.\n Is not needed. (Lukas)\n CXL/PCI: Introduce CXL uncorrectable protocol error recovery\n - Clean up port discovery in cxl_do_recovery() (Dave)\n - Add PCI_EXP_TYPE_RC_END to type check in cxl_report_error_detected()\n\nChanges in v10 -> v11:\n cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c\n - New patch\n CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS\n - New patch\n cxl/pci: Remove unnecessary CXL RCH handling helper functions\n - New patch\n cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditional block\n - New patch\n CXL/AER: Introduce rch_aer.c into AER driver for handling CXL RCH errors\n - Remove changes in code-split and move to earlier, new patch\n - Add #include to cxl_ras.c\n - Move cxl_rch_handle_error() & cxl_rch_enable_rcec() declarations from pci.h\n to aer.h, more localized.\n - Introduce CONFIG_CXL_RCH_RAS, includes Makefile changes, ras.c ifdef changes\n CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h\n - New patch\n PCI/CXL: Introduce pcie_is_cxl()\n - Amended set_pcie_cxl() to check for Upstream Port's and EP's parent\n downstream port by calling set_pcie_cxl(). (Dan)\n - Retitle patch: 'Add' -> 'Introduce'\n - Add check for CXL.mem and CXL.cache (Alejandro, Dan)\n PCI/AER: Report CXL or PCIe bus error type in trace logging\n - Remove duplicate call to trace_aer_event() (Shiju)\n - Added Dan William's and Dave Jiang's reviewed-by\n CXL/AER: Update PCI class code check to use FIELD_GET()\n - Add #include to cxl_ras.c (Terry)\n - Removed line wrapping at \"(CXL 3.2, 8.1.12.1)\". (Jonathan)\n cxl/pci: Log message if RAS registers are unmapped\n - Added Dave Jiang's review-by (Terry)\n cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports\n - Updated CE and UCE trace routines to maintian consistent TP_Struct ABI\n and unchanged TP_printk() logging. (Shiju, Alison)\n cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors\n - Added Dave Jiang and Jonathan Cameron's review-by\n - Changes moved to core/ras.c\n cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers\n - Use local pointer for readability in cxl_switch_port_init_ras() (Jonathan Cameron)\n - Rename port to be ep in cxl_endpoint_port_init_ras() (Dave Jiang)\n - Rename dport to be parent_dport in cxl_endpoint_port_init_ras()\n and cxl_switch_port_init_ras() (Dave Jiang)\n - Port helper changes were in cxl/port.c, now in core/ras.c (Dave Jiang)\n cxl/pci: Introduce CXL Endpoint protocol error handlers\n - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonathan)\n - cxl_error_detected() - Remove extra line (Shiju)\n - Changes moved to core/ras.c (Terry)\n - cxl_error_detected(), remove 'ue' and return with function call. (Jonathan)\n - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition\n - Move #include \"pci.h from cxl.h to core.h (Terry)\n - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry)\n CXL/AER: Introduce cxl_aer.c into AER driver for forwarding CXL errors\n - Move RCH implementation to cxl_rch.c and RCH declarations to pci/pci.h. (Terry)\n - Introduce 'struct cxl_proto_err_kfifo' containing semaphore, fifo,\n and work struct. (Dan)\n - Remove embedded struct from cxl_proto_err_work (Dan)\n - Make 'struct work_struct *cxl_proto_err_work' definition static (Jonathan)\n - Add check for NULL cxl_proto_err_kfifo to determine if CXL driver is\n not registered for workqueue. (Dan)\n PCI/AER: Dequeue forwarded CXL error\n - Reword patch commit message to remove RCiEP details (Jonathan)\n - Add #include (Terry)\n - is_cxl_rcd() - Fix short comment message wrap (Jonathan)\n - is_cxl_rcd() - Combine return calls into 1 (Jonathan)\n - cxl_handle_proto_error() - Move comment earlier (Jonathan)\n - Usse FIELD_GET() in discovering class code (Jonathan)\n - Remove BDF from cxl_proto_err_work_data. Use 'struct pci_dev *' (Dan)\n CXL/PCI: Introduce CXL Port protocol error handlers\n - Removed check for PCI_EXP_TYPE_RC_END in cxl_report_error_detected() (Terry)\n - Update is_cxl_error() to check for acceptable PCI EP and port types\n CXL/PCI: Export and rename merge_result() to pci_ers_merge_result()\n - pci_ers_merge_result() - Change export to non-namespace and rename\n to be pci_ers_merge_result() (Jonathan)\n - Move pci_ers_merge_result() definition to pci.h. Needs pci_ers_result (Terry)\n CXL/PCI: Introduce CXL uncorrectable protocol error recovery\n - pci_ers_merge_results() - Move to earlier patch\n CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup\n - Remove guard() in cxl_mask_proto_interrupts(). Observed device lockup/block\n during testing. (Terry)\n\nChanges in v9 -> v10:\n - Add drivers/pci/pcie/cxl_aer.c\n - Add drivers/cxl/core/native_ras.c\n - Change cxl_register_prot_err_work()/cxl_unregister_prot_err_work to return void\n - Check for pcie_ports_native in cxl_do_recovery()\n - Remove debug logging in cxl_do_recovery()\n - Update PCI_ERS_RESULT_PANIC definition to indicate is CXL specific\n - Revert trace logging changes: name,parent -> memdev,host.\n - Use FIELD_GET() to check for EP class code (cxl_aer.c & native_ras.c).\n - Change _prot_ to _proto_ everywhere\n - cxl_rch_handle_error_iter(), check if driver is cxl_pci_driver\n - Remove cxl_create_prot_error_info(). Move logic into forward_cxl_error()\n - Remove sbdf_to_pci() and move logic into cxl_handle_proto_error()\n - Simplify/refactor get_pci_cxl_host_dev()\n - Simplify/refactor cxl_get_ras_base()\n - Move patch 'Remove unnecessary CXL Endpoint handling helper functions' to front\n - Update description for 'CXL/PCI: Introduce CXL Port protocol error\n handlers' with why state is not used to determine handling\n - Introduce cxl_pci_drv_bound() and call from cxl_rch_handle_error_iter()\n Changes in v8 -> v9:\n - Updated reference counting to use pci_get_device()/pci_put_device() in\n cxl_disable_prot_errors()/cxl_enable_prot_errors\n - Refactored cxl_create_prot_err_info() to fix reference counting\n - Removed 'struct cxl_port' driver changes for error handler. Instead\n check for CXL device type (EP or Port device) and call handler\n - Make pcie_is_cxl() static inline in include/linux/linux.h\n - Remove NULL check in create_prot_err_info()\n - Change success return in cxl_ras_init() to use hardcoded 0\n - Changed 'struct work_struct cxl_prot_err_work' declaration to static\n - Change to use rate limited log with dev anchor in forward_cxl_error()\n - Refactored forward-cxl_error() to remove severity auto variable\n - Changed pci_aer_clear_nonfatal_status() to be static inline for\n !(CONFIG_PCIEAER)\n - Renamed merge_result() to be cxl_merge_result()\n - Removed 'ue' condition in cxl_error_detected()\n - Updated 2nd parameter in call to __cxl_handle_cor_ras()/__cxl_handle_ras()\n in unify patch\n - Added log message for failure while assigning interrupt disable callback\n - Updated pci_aer_mask_internal_errors() to use pci_clear_and_set_config_dword()\n - Simplified patch titles for clarity\n - Moved CXL error interrupt disabling into cxl/core/port.c with CXL Port\n teardown\n - Updated 'struct cxl_port_err_info' to only contain sbdf and severity\n Removed everything else.\n - Added pdev and CXL device get_device()/put_device() before calling handlers\n\nChanges in v7 -> v8:\n [Dan] Use kfifo. Move handling to CXL driver. AER forwards error to CXL\n driver\n [Dan] Add device reference incrementors where needed throughout\n [Dan] Initiate CXL Port RAS init from Switch Port and Endpoint Port init\n [Dan] Combine CXL Port and CXL Endpoint trace routine\n [Dan] Introduce aer_info::is_cxl. Use to indicate CXL or PCI errors\n [Jonathan] Add serial number for all devices in trace\n [DaveJ] Move find_cxl_port() change into patch using it\n [Terry] Move CXL Port RAS init into cxl/port.c\n [Terry] Moved kfifo functions into cxl/core/ras.c\n\nChanges in v6 -> v7:\n [Terry] Move updated trace routine call to later patch. Was causing build\n error.\n\nChanges in v5 -> v6:\n [Ira] Move pcie_is_cxl(dev) define to a inline function\n [Ira] Update returning value from pcie_is_cxl_port() to bool w/o cast\n [Ira] Change cxl_report_error_detected() cleanup to return correct bool\n [Ira] Introduce and use PCI_ERS_RESULT_PANIC\n [Ira] Reuse comment for PCIe and CXL recovery paths\n [Jonathan] Add type check in for cxl_handle_cor_ras() and cxl_handle_ras()\n [Jonathan] cxl_uport/dport_init_ras_reporting(), added a mutex.\n [Jonathan] Add logging example to patches updating trace output\n [Jonathan] Make parameter 'const' to eliminate for cast in match_uport()\n [Jonathan] Use __free() in cxl_pci_port_ras()\n [Terry] Add patch to log the PCIe SBDF along with CXL device name\n [Terry] Add patch to handle CXL endpoint and RCH DP errors as CXL errors\n [Terry] Remove patch w USP UCE fatal support @ aer_get_device_error_info()\n [Terry] Rebase to cxl/next commit 5585e342e8d3 (\"cxl/memdev: Remove unused partition values\")\n [Gregory] Pre-initialize pointer to NULL in cxl_pci_port_ras()\n [Gregory] Move AER driver bus name detection to a static function\n\nChanges in v4 -> v5:\n [Alejandro] Refactor cxl_walk_bridge to simplify 'status' variable usage\n [Alejandro] Add WARN_ONCE() in __cxl_handle_ras() and cxl_handle_cor_ras()\n [Ming] Remove unnecessary NULL check in cxl_pci_port_ras()\n [Terry] Add failure check for call to to_cxl_port() in cxl_pci_port_ras()\n [Ming] Use port->dev for call to devm_add_action_or_reset() in\n cxl_dport_init_ras_reporting() and cxl_uport_init_ras_reporting()\n [Jonathan] Use get_device()/put_device() to prevent race condition in\n cxl_clear_port_error_handlers() and cxl_clear_port_error_handlers()\n [Terry] Commit message cleanup. Capitalize keywords from CXL and PCI\n specifications\n\nChanges in v3 -> v4:\n [Lukas] Capitalize PCIe and CXL device names as in specifications\n [Lukas] Move call to pcie_is_cxl() into cxl_port_devsec()\n [Lukas] Correct namespace spelling\n [Lukas] Removed export from pcie_is_cxl_port()\n [Lukas] Simplify 'if' blocks in cxl_handle_error()\n [Lukas] Change panic message to remove redundant 'panic' text\n [Ming] Update to call cxl_dport_init_ras_reporting() in RCH case\n [lkp@intel] 'host' parameter is already removed. Remove parameter description too.\n [Terry] Added field description for cxl_err_handlers in pci.h comment block\n\nChanges in v1 -> v2:\n [Jonathan] Remove extra NULL check and cleanup in cxl_pci_port_ras()\n [Jonathan] Update description to DSP map patch description\n [Jonathan] Update cxl_pci_port_ras() to check for NULL port\n [Jonathan] Dont call handler before handler port changes are present (patch order)\n [Bjorn] Fix linebreak in cover sheet URL\n [Bjorn] Remove timestamps from test logs in cover sheet\n [Bjorn] Retitle AER commits to use \"PCI/AER:\"\n [Bjorn] Retitle patch#3 to use renaming instead of refactoring\n [Bjorn] Fix base commit-id on cover sheet\n [Bjorn] Add VH spec reference/citation\n [Terry] Removed last 2 patches to enable internal errors. Is not needed\n because internal errors are enabled in AER driver.\n [Dan] Create cxl_do_recovery() and pci_driver::cxl_err_handlers.\n [Dan] Use kernel panic in CXL recovery\n [Dan] cxl_port_hndlrs -> cxl_port_error_handlers\n\n\n\n\n\n\n\n\nDan Williams (3):\n cxl/ras: Unify Endpoint and Port AER trace events\n cxl: Rename find_cxl_port() to find_cxl_port_by_dport()\n cxl: Limit CXL-CPER kfifo registration functions scope\n\nTerry Bowman (8):\n PCI/AER: Introduce AER-CXL Kfifo\n cxl: Use common CPER handling for all CXL devices\n PCI: Establish common CXL Port protocol error flow\n PCI/CXL: Add RCH support to CXL handlers\n cxl: Remove Endpoint AER correctable handler\n cxl: Update Endpoint AER uncorrectable handler\n PCI/CXL: Mask/Unmask CXL protocol errors\n Documentation: cxl: Document CXL protocol error handling\n\n Documentation/driver-api/cxl/index.rst | 1 +\n .../cxl/linux/protocol-error-handling.rst | 440 ++++++++++++++++++\n MAINTAINERS | 2 +\n drivers/acpi/apei/ghes.c | 27 +-\n drivers/cxl/core/core.h | 22 +-\n drivers/cxl/core/port.c | 22 +-\n drivers/cxl/core/ras.c | 351 +++++++++-----\n drivers/cxl/core/ras_rch.c | 10 +-\n drivers/cxl/core/trace.h | 76 +--\n drivers/cxl/cxlpci.h | 11 +-\n drivers/cxl/pci.c | 7 +-\n drivers/pci/pci.c | 1 +\n drivers/pci/pci.h | 2 -\n drivers/pci/pcie/Makefile | 1 +\n drivers/pci/pcie/aer.c | 33 +-\n drivers/pci/pcie/aer_cxl_rch.c | 17 +-\n drivers/pci/pcie/aer_cxl_vh.c | 149 ++++++\n drivers/pci/pcie/portdrv.h | 4 +\n include/cxl/event.h | 10 +-\n include/linux/aer.h | 32 ++\n include/linux/pci.h | 2 +\n 21 files changed, 959 insertions(+), 261 deletions(-)\n create mode 100644 Documentation/driver-api/cxl/linux/protocol-error-handling.rst\n create mode 100644 drivers/pci/pcie/aer_cxl_vh.c\n\n\nbase-commit: 7fd2df204f342fc17d1a0bfcd474b24232fb0f32"}