{"id":2230927,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2230927/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/cover/20260430084414.1354490-1-richard.genoud@bootlin.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430084414.1354490-1-richard.genoud@bootlin.com>","list_archive_url":null,"date":"2026-04-30T08:43:53","name":"[00/20] Introduce resume for J7xx SoCs","submitter":{"id":88519,"url":"http://patchwork.ozlabs.org/api/1.2/people/88519/?format=json","name":"Richard Genoud (TI)","email":"richard.genoud@bootlin.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/cover/20260430084414.1354490-1-richard.genoud@bootlin.com/mbox/","series":[{"id":502237,"url":"http://patchwork.ozlabs.org/api/1.2/series/502237/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502237","date":"2026-04-30T08:43:53","name":"Introduce resume for J7xx SoCs","version":1,"mbox":"http://patchwork.ozlabs.org/series/502237/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2230927/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=PzQKU/dx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.b=\"PzQKU/dx\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com","phobos.denx.de;\n spf=pass smtp.mailfrom=richard.genoud@bootlin.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5nm309R6z1xqf\n\tfor ; Thu, 30 Apr 2026 18:44:34 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 2D36984653;\n\tThu, 30 Apr 2026 10:44:32 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id ADDB48466B; Thu, 30 Apr 2026 10:44:30 +0200 (CEST)","from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3823A8460D\n for ; Thu, 30 Apr 2026 10:44:28 +0200 (CEST)","from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233])\n by smtpout-04.galae.net (Postfix) with ESMTPS id 9AADAC5CD62;\n Thu, 30 Apr 2026 08:45:11 +0000 (UTC)","from mail.galae.net (mail.galae.net [212.83.136.155])\n by smtpout-01.galae.net (Postfix) with ESMTPS id 0E52260495;\n Thu, 30 Apr 2026 08:44:27 +0000 (UTC)","from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id EA5191072B7A9;\n Thu, 30 Apr 2026 10:44:22 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n t=1777538665; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding; bh=YNC93x7U+AnXgwcex1n/EFt/aXgg2QYvocUoCCqmNOI=;\n b=PzQKU/dxIIj1zdDORpuWLmtsUw84ebnfjzurjCM8hIP1hHVTWzOq7vd5QRVcMo0bNLJ8B0\n T6EIFsUPYo2WjTumGDbUp+qMERxzVlIQitteBczTZqeFsEFgOCG13xwW61MsrBQ9agUATS\n n/JdzAMjDlFvTfnTemUfQcNX5o4BtC9N56PZUQvABnl9W1hH2QliLxpxCRQlg9VeBWos1A\n j2WlKZquJeeLu+uqGeYNecJjsFGdttkQ3DFHJ7yXeLdury8mEf3wSK6mBKGcdTzhDLG69d\n BzZ4j3LWIZgNdP/nn43XYzdwfCl7JAm/rIyGTa41fBz1tFKyOpzbtb5VFR+CGA==","From":"\"Richard Genoud (TI)\" ","To":"Tom Rini , Manorit Chawdhry ,\n Apurva Nandan , \"Andrew F . Davis\" ,\n Vignesh Raghavendra , Bryan Brattlof ,\n Vaishnav Achath , Jayesh Choudhary ,\n Simon Glass , Alper Nebi Yasak ","Cc":"Markus Schneider-Pargmann ,\n Udit Kumar ,\n Abhash Kumar ,\n Thomas Richard ,\n Gregory CLEMENT ,\n Thomas Petazzoni ,\n Richard Genoud , u-boot@lists.denx.de","Subject":"[PATCH 00/20] Introduce resume for J7xx SoCs","Date":"Thu, 30 Apr 2026 10:43:53 +0200","Message-ID":"<20260430084414.1354490-1-richard.genoud@bootlin.com>","X-Mailer":"git-send-email 2.47.3","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Last-TLS-Session-Version":"TLSv1.3","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"This series allows J7200/J721e/J721s2/J784s4/J722s to resume from\nsuspend.\n\nOn those SoCs, a magic value is set in a PMIC register by the DM\nfirmware just before suspend, then everything but the PMIC and DDR is\npowered off.\nAt resume/boot time, the magic value has to be read back by U-Boot SPL in\norder to know if we are indeed in a resume situation.\nThat's the purpose of j7xx_board_is_resuming() introduced here.\n\nThen, if the SoC is resuming, the DDR has to be be brought out of\nretention, at full speed and get out of low power mode.\nBetween those steps, the DDR_RET pin has to be de-asserted. But the\nDDR_RET pins of all DDR chips are tied together on a single GPIO, so\nit's impossible to resume one DDR chip after the other, they must be all\nresumed at once.\nThat's why it's orchestrated from board_init_f() and not in the k3ddrss\ndriver.\n\nOnce the DDR is fully functional, the next steps are:\n - retrieve the LPM memory region from DTS\n - authenticate certificates from LPM memory region and apply firewalls\n - ask TIFS to restore TFA and its own minimal context\n - start TFA on remote proc\n - load and jump to DM\n\nPatch 1 adds a missing config option for j784s4\nPatches 2-6 add the resume detection for all SoCs\nPatches 7-9 add the DDR resume sequence for all SoCs\nPatches 10-15 add the resume flow for all SoCs\nPatch 16 updates the pm-cfg and schema to a new version\nPatch 17 detects IO+DDR resume state for j7200/j784s4\nPatch 18 stores the wakeup reason in MCU_PSRAM0_RAM for j7200/j784s4\nPatch 19 removes now unneeded background firewall on DDR for j7200/j784s4\nPatch 20 extends the firewall for ATF region to TIFS\n\nTested on J722s HS-FS, J7200 GP, J784s4 GP, J721s2 GP\n\nBEWARE: This series is based on v2026.04 + AM62 LPM series:\nhttps://lore.kernel.org/u-boot/20260105-topic-am62-ioddr-v2025-04-rc1-v9-0-7e33f2c77dbf@baylibre.com/\n\nIt needs lpm_memory_regions described in DTS:\nhttps://lore.kernel.org/lkml/20260427160326.370415-1-richard.genoud@bootlin.com/\n\nAbhash Kumar Jha (3):\n arm: mach-k3: Update pm-boardcfg for all k3 platforms\n board: evm: Enable de-isolation of IOs at resume for j7200 and j784s4\n board: ti: evm: Store wakeup reason on scratchpad memory\n\nPrasanth Babu Mantena (3):\n firmware: ti_sci: add low power mode operations\n arm: dts: k3-j7200: Remove background firewall on DDR\n arm: dts: k3-j7200: Extend firewall for ATF region to TIFS\n\nRichard Genoud (TI) (9):\n configs: j784s4_evm_r5: enable TI_SCI_POWER_DOMAIN\n global: k3: use gd to store the resume state\n board: ti: j784s4: Add resume detection\n board: ti: j722s: Add resume detection\n ram: k3-ddrss: Add j722s DDR resume sequence\n ram: k3-ddrss: support j784s4/j721e/j721s2 DDR resume\n mach-k3: r5: common: add helper functions needed in LPM resume\n sequence\n arm: mach-k3: j784s4: Enable LPM resume flow for J784s4/J742s2 SOCs\n arm: mach-k3: j722s: Enable LPM resume flow\n\nThomas Richard (TI) (5):\n board: ti: j721e: Add resume detection for J721e/J7200\n board: ti: j721s2: Add resume detection\n ram: k3-ddrss: Add exit retention support\n arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC\n arm: mach-k3: j721s2: Enable LPM resume flow\n\n arch/arm/dts/k3-binman.dtsi | 18 +-\n arch/arm/dts/k3-j7200-binman.dtsi | 18 +-\n arch/arm/dts/k3-j722s-r5-evm.dts | 4 +\n arch/arm/dts/k3-security.h | 1 +\n arch/arm/include/asm/global_data.h | 19 ++\n arch/arm/mach-k3/common.h | 16 +\n .../arm/mach-k3/include/mach/j721e_hardware.h | 12 +\n .../mach-k3/include/mach/j784s4_hardware.h | 11 +\n arch/arm/mach-k3/include/mach/k3-ddr.h | 16 +\n arch/arm/mach-k3/include/mach/security.h | 1 +\n arch/arm/mach-k3/j721e/j721e_init.c | 64 ++++\n arch/arm/mach-k3/j721s2/j721s2_init.c | 73 ++++-\n arch/arm/mach-k3/j722s/j722s_init.c | 11 +-\n arch/arm/mach-k3/j784s4/j784s4_init.c | 70 ++++-\n arch/arm/mach-k3/lpm-common.h | 15 +\n arch/arm/mach-k3/r5/Kconfig | 4 +\n arch/arm/mach-k3/r5/Makefile | 1 +\n arch/arm/mach-k3/r5/common.c | 17 +-\n arch/arm/mach-k3/r5/lpm-common.c | 228 +++++++++++++++\n arch/arm/mach-k3/schema.yaml | 195 ++++++++++---\n arch/arm/mach-k3/security.c | 64 ++++\n board/phytec/phycore_am62ax/pm-cfg.yaml | 7 +-\n board/ti/am62ax/pm-cfg.yaml | 7 +-\n board/ti/am62px/pm-cfg.yaml | 7 +-\n board/ti/am62x/pm-cfg.yaml | 7 +-\n board/ti/am64x/pm-cfg.yaml | 5 +-\n board/ti/am65x/pm-cfg.yaml | 7 +-\n board/ti/common/k3-lpm.h | 22 ++\n board/ti/j7200/pm-cfg.yaml | 92 +++++-\n board/ti/j721e/evm.c | 75 +++++\n board/ti/j721e/pm-cfg.yaml | 92 +++++-\n board/ti/j721s2/evm.c | 37 +++\n board/ti/j721s2/pm-cfg.yaml | 94 +++++-\n board/ti/j722s/evm.c | 51 ++++\n board/ti/j722s/pm-cfg.yaml | 7 +-\n board/ti/j784s4/evm.c | 78 +++++\n board/ti/j784s4/pm-cfg.yaml | 94 +++++-\n configs/j784s4_evm_r5_defconfig | 1 +\n drivers/firmware/ti_sci.c | 179 ++++++++++++\n drivers/firmware/ti_sci.h | 92 ++++++\n drivers/ram/k3-ddrss/k3-ddrss.c | 273 ++++++++++++++++++\n drivers/ram/k3-ddrss/lpddr4_k3_reg.h | 94 ++++++\n include/linux/soc/ti/ti_sci_protocol.h | 8 +\n tools/binman/etype/ti_board_config.py | 4 +-\n 44 files changed, 2088 insertions(+), 103 deletions(-)\n create mode 100644 arch/arm/mach-k3/lpm-common.h\n create mode 100644 arch/arm/mach-k3/r5/lpm-common.c\n create mode 100644 board/ti/common/k3-lpm.h\n create mode 100644 drivers/ram/k3-ddrss/lpddr4_k3_reg.h"}