{"id":2227867,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2227867/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260424201842.176953-1-junjie.cao@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424201842.176953-1-junjie.cao@intel.com>","list_archive_url":null,"date":"2026-04-24T20:18:40","name":"[v2,0/2] intel_iommu: fix guest-triggerable assert in MMIO handlers","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/1.2/people/91537/?format=json","name":"Junjie Cao","email":"junjie.cao@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260424201842.176953-1-junjie.cao@intel.com/mbox/","series":[{"id":501352,"url":"http://patchwork.ozlabs.org/api/1.2/series/501352/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501352","date":"2026-04-24T20:18:40","name":"intel_iommu: fix guest-triggerable assert in MMIO handlers","version":2,"mbox":"http://patchwork.ozlabs.org/series/501352/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2227867/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=hlL/Ypw2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2Bm118Ylz1yDD\n\tfor ; Fri, 24 Apr 2026 22:17:03 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGFSI-0002Zo-LR; Fri, 24 Apr 2026 08:16:24 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGFS0-0002WA-5d\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 08:16:09 -0400","from mgamail.intel.com ([198.175.65.18])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGFRx-0002Ba-KC\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 08:16:03 -0400","from fmviesa005.fm.intel.com ([10.60.135.145])\n by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Apr 2026 05:15:57 -0700","from junjie-optiplex-micro-plus-7010.bj.intel.com ([10.238.152.98])\n by fmviesa005-auth.fm.intel.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2026 05:15:55 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777032961; x=1808568961;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=0bAUA6abi1M7sQpo2yAtJklfJJMcJmkICMcIRGpxe18=;\n b=hlL/Ypw2fFCyQ2AnogcMmYKItYQC4WRVn25jvLf/+yOYJwWXsM0Anofo\n COcz77NLgMpTdTtJ+VpK8mPKFxVAevwsgxn34gHE5DSbn2RYwVR203cqg\n +gd+V2ZsJuuLrhawpQXG9l4oz/b0Ed4LfN31KKstNB8RmAkCTsa72FzzO\n wqkecsfcSocJElaf7ENhJoh6pVvTUGiilO2ynRtDGsBwz1Y0oZZtYVqTi\n jwAppai/N9JrwORLjIWe7JT5x6xR/DIX8hk1QZ+4AvSsxXX77lpVGygJZ\n DqQthGF6W5ti2fixT15Xko1pq/ToKJskjyRIOltRpwKB+Hljclu+XA+3T A==;","X-CSE-ConnectionGUID":["MaCwuLRLQqiye/6xxjkDdQ==","007NdqGXQwCI7ZUMndmVkg=="],"X-CSE-MsgGUID":["XdePhQmmTAu0iPCkMkmlsg==","iHuhxzKFRneswVZowg3nhw=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11765\"; a=\"78029972\"","E=Sophos;i=\"6.23,196,1770624000\"; d=\"scan'208\";a=\"78029972\"","E=Sophos;i=\"6.23,196,1770624000\"; d=\"scan'208\";a=\"237935749\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"qemu-devel@nongnu.org","Cc":"junjie.cao@intel.com, mst@redhat.com, jasowang@redhat.com,\n yi.l.liu@intel.com, clement.mathieu--drif@bull.com, philmd@linaro.org,\n zhenzhong.duan@intel.com","Subject":"[PATCH v2 0/2] intel_iommu: fix guest-triggerable assert in MMIO\n handlers","Date":"Sat, 25 Apr 2026 04:18:40 +0800","Message-ID":"<20260424201842.176953-1-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.18;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-24","X-Spam_score":"-2.5","X-Spam_bar":"--","X-Spam_report":"(-2.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_06_12=1.947,\n DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1,\n DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"An 8-byte guest access to any 32-bit-only VT-d register hits\nassert(size == 4) and aborts QEMU. Found by fuzzing with\ngeneric-fuzz; 24 distinct crash inputs all share the same root cause.\n\nv1: https://lore.kernel.org/all/20260420170523.17908-1-junjie.cao@intel.com/\nv2: Per Philippe's suggestion, widen .impl.min_access_size to 8\ninstead of replacing asserts with guest-error checks. This lets the\nmemory subsystem always pass size == 8 to the handler, eliminating\nall 25 asserts and every size-based branch.\n\nJunjie Cao (2):\n intel_iommu: widen impl.min_access_size to 8 to fix MMIO abort\n tests/qtest: add 8-byte MMIO access sweep for intel-iommu\n\n hw/i386/intel_iommu.c | 121 +++++++--------------------------\n tests/qtest/intel-iommu-test.c | 30 ++++++++\n 2 files changed, 53 insertions(+), 98 deletions(-)"}