{"id":2224537,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2224537/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1776437127.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-17T14:49:30","name":"[v10,0/2] Generate strided vector loads/stores with tcg nodes","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1776437127.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":500357,"url":"http://patchwork.ozlabs.org/api/1.2/series/500357/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500357","date":"2026-04-17T14:49:31","name":"Generate strided vector loads/stores with tcg nodes","version":10,"mbox":"http://patchwork.ozlabs.org/series/500357/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2224537/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=PXZorjOh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::a42;\n envelope-from=chao.liu.zevorn@gmail.com; helo=mail-vk1-xa42.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Hi Alistair,\n\nIn patch v10:\n\n- Update the email address of the patch submitter.\n- Rebase on the latest riscv-to-apply.next branch.\n\nHistory of changes:\n\npatch v9:\n- Simplify the implementation of gen_check_vext_elem_mask():\n remove the `mask` argument, compute the mask directly inside the function,\n and eliminate redundant code.\n- Limit the bit width to 8 bits when loading the mask from memory.\n- Remove the `vreg` argument in gen_ldst_vreg().\n https://lore.kernel.org/qemu-devel/cover.1758006834.git.chao.liu@zevorn.cn/\n\npatch v8:\n- Use the right TCGv type for each variable — for example, make mask_elem\n type TCGv_i64.\n- Use tcg_gen_trunc_i64_ptr() to change TCGv types — don't use C-style\n casting.\n- Use TCG_COND_TSTNE, not TCG_COND_NE in tcg_gen_brcond_i64() to represent:\n if (vext_elem_mask(v0, i) != 0)\n https://lore.kernel.org/qemu-devel/cover.1757690407.git.chao.liu@zevorn.cn/\n\npatch v7:\n- Standardize the subject line of patch 1 and remove the trailing period.\n- Split into sub-functions to improve the patch's code readability and\n facilitate review.\n- Use more faster TCG ops, use tcg_gen_andi_tl() instead of tcg_gen_rem_tl().\n- Add a tested-by signature for patch 2, as Eric has already tested it.\n https://lore.kernel.org/qemu-devel/cover.1756975571.git.chao.liu@zevorn.cn/\n\npatch v6:\n- If a strided vector memory access instruction has non-zero vstart,\n check it through vlse/vsse helpers function.\n- Adjust the tcg test Makefile.\n https://lore.kernel.org/qemu-devel/cover.1756906528.git.chao.liu@zevorn.cn/\n\nPatch v5:\n- Removed the redundant call to mark_vs_dirty(s) within the\n gen_ldst_stride_main_loop() function.\n https://lore.kernel.org/qemu-riscv/cover.1755609029.git.chao.liu@zevorn.cn/\n\nPatch v4:\n- Use ctz32() replace to for-loop\n https://lore.kernel.org/qemu-devel/cover.1755333616.git.chao.liu@yeah.net/\n\nPatch v3:\n- Fix the get_log2() function:\n https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao.liu@yeah.net/T/#t\n- Add test for vlsseg8e32 instruction.\n- Rebase on top of the latest master.\n\nPatch v2:\n- Split the TCG node emulation of the complex strided load/store operation into\n two separate functions to simplify the implementation:\n https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.savini@embecosm.com/\n\nPatch v1:\n- Paolo submitted the initial version of the patch.\n https://lore.kernel.org/qemu-devel/20250211182056.412867-1-paolo.savini@embecosm.com/\n\n\nThanks,\nChao\n\nChao Liu (2):\n target/riscv: Use tcg nodes for strided vector ld/st generation\n tests/tcg/riscv64: Add test for vlsseg8e32 instruction\n\n target/riscv/insn_trans/trans_rvv.c.inc | 354 ++++++++++++++++++++--\n tests/tcg/riscv64/Makefile.softmmu-target | 7 +-\n tests/tcg/riscv64/test-vlsseg8e32.S | 107 +++++++\n 3 files changed, 450 insertions(+), 18 deletions(-)\n create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S\n\n--\n2.53.0"}