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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-B4-Tracking":"v=1; b=H4sIAF0T4mkC/32NQQrCMBBFr1JmbSQJ2lRX3kNKCZlpO2IbmZSil\n Nzd2AO4fA/++xskEqYE12oDoZUTx7mAPVQQRj8PpBgLg9W21idTq8fkg+rJL51M1A3Iyplg0SL\n Wzmkou5dQz++9eW8Lj5yWKJ/9YjU/+6+2GqUVXnqvXWMIz83tybOXeIwyQJtz/gIEtRjkswAAA\n A==","To":"qemu-devel@nongnu.org","Cc":"Peter Maydell ,\n Richard Henderson , qemu-arm@nongnu.org,\n Jim MacArthur ","X-Mailer":"b4 0.13.0","Received-SPF":"pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Adds FEAT_RME_GDI, some extra cases to arm_granule_protection_check,\nand a very basic TCG test to check the prerequisites of FEAT_RME_GDI:\nFEAT_RME and FEAT_RME_GPC2.\n\nFEAT_RME_GDI is not enabled yet as no functional support has been\nadded; it can easily be enabled in cpu_arm_set_rme in future.\n\nIn the future we should correctly set bits in the fault address\nregisters such as PFAR_EL2, but I don't see any apparent support for\nthese in the existing GPT mechanism. Testing this also gets tricky as\nI think this would have to be done from EL3 (e.g. by modifying\ntest_rme_virt.py)\n\nSigned-off-by: Jim MacArthur \n---\nChanges in v2:\n- arm_granule protection_check now checks SA, NSP, NA6, NA7 and\n goes to fault_fail if set for the appropriate GDI encoding.\n- New fields for GPCCR: SA, NSP, NA6, NA7 and GPCBW\n- Since we're touching AA64MMFR4, added in all the new fields not\n currently listed.\n- Link to v1: https://lore.kernel.org/qemu-devel/20260416-jmac-feat_rme_gdi-v1-0-d9fa0781ed58@linaro.org\n\n---\nJim MacArthur (4):\n target/arm/cpu-features.c: New fields in AA64MMFR4\n target/arm/cpu.h: New GPCCR fields\n target/arm/ptw.c: Add GDI spaces to the granule protection case\n tests/tcg/aarch64/system/rme_gdi.c: Very basic test of GDI\n\n target/arm/cpu-features.h | 8 ++++++\n target/arm/cpu.h | 5 ++++\n target/arm/ptw.c | 20 ++++++++++++++\n tests/tcg/aarch64/system/rme_gdi.c | 56 ++++++++++++++++++++++++++++++++++++++\n 4 files changed, 89 insertions(+)\n---\nbase-commit: da6c4fe60fee30dd77267764d55b38af9cb89d4b\nchange-id: 20260416-jmac-feat_rme_gdi-71c2d2dd6770\n\nBest regards,"}