{"id":2224254,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2224254/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/cover/20260417073452.23342-1-clamor95@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417073452.23342-1-clamor95@gmail.com>","list_archive_url":null,"date":"2026-04-17T07:34:51","name":"[v1,0/1] clk: tegra: support 48MHz clock for pll_p_out1","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/1.2/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/cover/20260417073452.23342-1-clamor95@gmail.com/mbox/","series":[{"id":500256,"url":"http://patchwork.ozlabs.org/api/1.2/series/500256/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500256","date":"2026-04-17T07:34:52","name":"clk: tegra: support 48MHz clock for pll_p_out1","version":1,"mbox":"http://patchwork.ozlabs.org/series/500256/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2224254/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ISfRekBt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported\nby kernel and causes BUG() early on. Fix this by adding 48MHz\nclock support for pll_p_out1 along with 48MHz support for pll_a,\nmain pll_p_out1 descendant.\n\nDmitry Osipenko (1):\n clk: tegra: support 48MHz clock for pll_p_out1\n\n drivers/clk/tegra/clk-pll.c | 1 +\n drivers/clk/tegra/clk-tegra114.c | 6 ++++--\n 2 files changed, 5 insertions(+), 2 deletions(-)"}