{"id":266,"url":"http://patchwork.ozlabs.org/api/1.1/patches/266/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1221253688-25864-2-git-send-email-galak@kernel.crashing.org/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.1/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<1221253688-25864-2-git-send-email-galak@kernel.crashing.org>","date":"2008-09-12T21:08:06","name":"powerpc: Fixes for CONFIG_PTE_64BIT for SMP support","commit_ref":"9bf2b5cdc5fe5e3136ceeecc85141765023ded6e","pull_url":null,"state":"accepted","archived":true,"hash":"c6f6e9b9475a9816775598950189a74df55ba80e","submitter":{"id":5,"url":"http://patchwork.ozlabs.org/api/1.1/people/5/?format=json","name":"Kumar Gala","email":"galak@kernel.crashing.org"},"delegate":{"id":9,"url":"http://patchwork.ozlabs.org/api/1.1/users/9/?format=json","username":"galak","first_name":"Kumar","last_name":"Gala","email":"galak@kernel.crashing.org"},"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1221253688-25864-2-git-send-email-galak@kernel.crashing.org/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/266/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/266/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork@ozlabs.org","linuxppc-dev@ozlabs.org"],"Delivered-To":["patchwork@ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from ozlabs.org (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id E425ADE2F1\n\tfor ; Sat, 13 Sep 2008 07:08:42 +1000 (EST)","from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(Client did not present a certificate)\n\tby ozlabs.org (Postfix) with ESMTPS id D444FDDF75\n\tfor ; Sat, 13 Sep 2008 07:08:15 +1000 (EST)","from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id m8CL8AJ9024757\n\tfor ; Fri, 12 Sep 2008 16:08:10 -0500"],"From":"Kumar Gala ","To":"linuxppc-dev@ozlabs.org","Subject":"[PATCH v4 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support","Date":"Fri, 12 Sep 2008 16:08:06 -0500","Message-Id":"<1221253688-25864-2-git-send-email-galak@kernel.crashing.org>","X-Mailer":"git-send-email 1.5.5.1","In-Reply-To":"<1221253688-25864-1-git-send-email-galak@kernel.crashing.org>","References":"<1221253688-25864-1-git-send-email-galak@kernel.crashing.org>","X-BeenThere":"linuxppc-dev@ozlabs.org","X-Mailman-Version":"2.1.11","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org","Errors-To":"linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org"},"content":"There are some minor issues with support 64-bit PTEs on a 32-bit processor\nwhen dealing with SMP.\n\n* We need to order the stores in set_pte_at to make sure the flag word\n is set second.\n* Change pte_clear to use pte_update so only the flag word is cleared\n* Added a WARN_ON to set_pte_at to ensure the pte isn't present for\n the 64-bit pte/SMP case (to ensure our assumption of this fact).\n\nSigned-off-by: Kumar Gala ","diff":"diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h\nindex 5d99b64..91c5895 100644\n--- a/arch/powerpc/include/asm/highmem.h\n+++ b/arch/powerpc/include/asm/highmem.h\n@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgpro\n #ifdef CONFIG_DEBUG_HIGHMEM\n \tBUG_ON(!pte_none(*(kmap_pte-idx)));\n #endif\n-\tset_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));\n+\t__set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));\n \tflush_tlb_page(NULL, vaddr);\n \n \treturn (void*) vaddr;\ndiff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h\nindex 6fe39e3..1b11955 100644\n--- a/arch/powerpc/include/asm/pgtable-ppc32.h\n+++ b/arch/powerpc/include/asm/pgtable-ppc32.h\n@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);\n \n #define pte_none(pte)\t\t((pte_val(pte) & ~_PTE_NONE_MASK) == 0)\n #define pte_present(pte)\t(pte_val(pte) & _PAGE_PRESENT)\n-#define pte_clear(mm,addr,ptep)\tdo { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)\n+#define pte_clear(mm, addr, ptep) \\\n+\tdo { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)\n \n #define pmd_none(pmd)\t\t(!pmd_val(pmd))\n #define\tpmd_bad(pmd)\t\t(pmd_val(pmd) & _PMD_BAD)\n@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,\n \treturn old;\n }\n #else /* CONFIG_PTE_64BIT */\n-/* TODO: Change that to only modify the low word and move set_pte_at()\n- * out of line\n- */\n static inline unsigned long long pte_update(pte_t *p,\n \t\t\t\t\t unsigned long clr,\n \t\t\t\t\t unsigned long set)\n@@ -652,16 +650,33 @@ static inline unsigned long long pte_update(pte_t *p,\n * On machines which use an MMU hash table we avoid changing the\n * _PAGE_HASHPTE bit.\n */\n-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,\n+\n+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,\n \t\t\t pte_t *ptep, pte_t pte)\n {\n #if _PAGE_HASHPTE != 0\n \tpte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);\n+#elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)\n+\t__asm__ __volatile__(\"\\\n+\t\tstw%U0%X0 %2,%0\\n\\\n+\t\teieio\\n\\\n+\t\tstw%U0%X0 %L2,%1\"\n+\t: \"=m\" (*ptep), \"=m\" (*((unsigned char *)ptep+4))\n+\t: \"r\" (pte) : \"memory\");\n #else\n \t*ptep = pte;\n #endif\n }\n \n+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,\n+\t\t\t pte_t *ptep, pte_t pte)\n+{\n+#if defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)\n+\tWARN_ON(pte_present(*ptep));\n+#endif\n+\t__set_pte_at(mm, addr, ptep, pte);\n+}\n+\n /*\n * 2.6 calls this without flushing the TLB entry; this is wrong\n * for our hash-based implementation, we fix that up here.\n","prefixes":[]}