{"id":2233389,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2233389/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260506015845.2306182-3-pan2.li@intel.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260506015845.2306182-3-pan2.li@intel.com>","date":"2026-05-06T01:57:11","name":"[v1,2/2] RISC-V: Add test for vec_duplicate + vmsgt.vv combine with GR2VR cost 0, 1 and 15","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c89d0bf2c1471cc7a4041f13cab1d002fc016526","submitter":{"id":86320,"url":"http://patchwork.ozlabs.org/api/1.1/people/86320/?format=json","name":"Li, Pan2","email":"pan2.li@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260506015845.2306182-3-pan2.li@intel.com/mbox/","series":[{"id":502962,"url":"http://patchwork.ozlabs.org/api/1.1/series/502962/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502962","date":"2026-05-06T01:57:10","name":"RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost","version":1,"mbox":"http://patchwork.ozlabs.org/series/502962/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233389/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233389/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=IN9qsqbc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=IN9qsqbc","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=intel.com","sourceware.org; spf=pass smtp.mailfrom=intel.com","sourceware.org; arc=none smtp.remote-ip=192.198.163.8"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g9XFG56J6z1y04\n\tfor ; Wed, 06 May 2026 20:49:22 +1000 (AEST)","from vm01.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id B363B4BA23FB\n\tfor ; Wed, 6 May 2026 10:49:20 +0000 (GMT)","from mgamail.intel.com (mgamail.intel.com [192.198.163.8])\n by sourceware.org (Postfix) with ESMTPS id EEB034BA799D\n for ; Wed, 6 May 2026 02:02:56 +0000 (GMT)","from fmviesa003.fm.intel.com ([10.60.135.143])\n by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 May 2026 19:02:56 -0700","from panli.sh.intel.com ([10.239.159.63])\n by fmviesa003.fm.intel.com with ESMTP; 05 May 2026 19:02:54 -0700"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org B363B4BA23FB","OpenDKIM Filter v2.11.0 sourceware.org EEB034BA799D"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org EEB034BA799D","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org EEB034BA799D","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1778032977; cv=none;\n b=FHHV7sV94s/yvLM8bRxkdqqeMfWVWC9hq0BQ24a1ZB6P2ohKYuyzmwlkBuGzDfPe909YVgj8djDb9KOh1U+Pwd6UgM6bl6OEhF7wnX8nJKT02JmvphmOdrKyew506wkmwDEatU6NPovEk6f3rcBUj9WefOEP2lZNt7SsiV9pnHs=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1778032977; c=relaxed/simple;\n bh=hYGrJer0oas6pnYi+m6psWi9c2Di8Cxkj2Re3+biN8c=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=WIpqdBKpiNfkqSvuVqRPnov24/eRT0NpUe5oah6f3lh2GejK3/qM0xSQ3XjBHWb/zxkMDvzWbrFR8xNUnPScSLFiJeKfZg64lc/WUB5IP+/zb36eCaLsuRp8dCRSRzjCjgP3vzzUc43W7grLub2axUyoDWHDhjwVlRN6/54lNeA=","ARC-Authentication-Results":"i=1; sourceware.org;\n dkim=pass (2048-bit key, unprotected)\n header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel\n header.b=IN9qsqbc","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1778032977; x=1809568977;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=hYGrJer0oas6pnYi+m6psWi9c2Di8Cxkj2Re3+biN8c=;\n b=IN9qsqbcz4TCxszDzZQW1FsnRaNedPI3ZnqO60bq4sH8x2jBYGQCs2O+\n d28yBI7easeGBLSYMtWAPhgoIjAMM+p1Ljfb47YxTt0n8qCq6NpV5k/mE\n 0M0mTvdCm78ej7M4JPJ++NgfVrSyw/VKIg6aFGa1xFxKMqyAl1jO3zcn9\n GjhXtQgLMIKcuh/C6B9lMQGBBeGVRaD6xW/Ys7pF6QT0/Wj6u3ilE1VSw\n o9bHL7Ew7pGW2lSDWhBY7+IH0zk+qxUsj+G3PbAG0fJwBKW/+Ch3vW14U\n vBNTakQdz9JwUpj2NW9ZeAQ30AD6hl/c5D61u1Zug6Wyvx3jNJFrjhJav Q==;","X-CSE-ConnectionGUID":["zxxm23SPR6eZuH52y0MNiQ==","YGKH815ZS1GMSfQa7wy22A=="],"X-CSE-MsgGUID":["kkvH8Hx2TDCi0vmjNx5wkA==","WYzpLuhjRl+JNtS2QqoSiQ=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11777\"; a=\"96484869\"","E=Sophos;i=\"6.23,218,1770624000\"; d=\"scan'208\";a=\"96484869\""],"X-ExtLoop1":"1","From":"pan2.li@intel.com","To":"gcc-patches@gcc.gnu.org","Cc":"juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com,\n rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com,\n Pan Li ","Subject":"[PATCH v1 2/2] RISC-V: Add test for vec_duplicate + vmsgt.vv combine\n with GR2VR cost 0, 1 and 15","Date":"Wed, 6 May 2026 09:57:11 +0800","Message-ID":"<20260506015845.2306182-3-pan2.li@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260506015845.2306182-1-pan2.li@intel.com>","References":"<20260506015845.2306182-1-pan2.li@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Pan Li \n\nAdd asm dump check and run test for vec_duplicate + vmsgt.vv\ncombine to vmsgt.vx, with the GR2VR cost is 0, 2 and 15.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check\n\tfor vmsgt.vx.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test\n\thelper macros.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test\n\tdata for run test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c: New test.\n\nSigned-off-by: Pan Li \n---\n .../riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary.h | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 ++++++++++++++++++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c | 15 ++\n 18 files changed, 209 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c","diff":"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c\nindex 683e7cebb28..b27bb338ee2 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c\nindex 07dcc2ec7e5..bc9b80f67cd 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c\nindex b30fe640d21..9b8de9cfea1 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c\n@@ -34,3 +34,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c\nindex 01b426afbfb..2e6ec208858 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */\n /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */\n+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c\nindex 532e1884aea..2d8263e0487 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c\nindex 5ed2711c032..bacf86c296f 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c\nindex b494695098e..e32719036d0 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c\nindex 8fdee21f931..aee6563b07b 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c\nindex 841b88e4c2c..2371d3fe250 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c\nindex e80fdcc7357..4b343f66aec 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c\nindex 548a3218e7f..5b8b853c320 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c\nindex eb10722f2d2..407261aad74 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c\n@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)\n /* { dg-final { scan-assembler-not {vmsne.vx} } } */\n /* { dg-final { scan-assembler-not {vmslt.vx} } } */\n /* { dg-final { scan-assembler-not {vmsle.vx} } } */\n+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h\nindex ff6b7f6542d..2291d9e9601 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h\n@@ -406,6 +406,7 @@ DEF_AVG_CEIL(int32_t, int64_t)\n DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \\\n DEF_VX_BINARY_CASE_0_WRAP(T, <, lt) \\\n DEF_VX_BINARY_CASE_0_WRAP(T, <=, le) \\\n+ DEF_VX_BINARY_CASE_0_WRAP(T, >, gt) \\\n DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \\\n DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \\\n DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \\\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h\nindex 952c8b49ecd..3cccd65b749 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h\n@@ -7110,4 +7110,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, gtu)[][3][N] =\n },\n };\n \n+int8_t TEST_BINARY_DATA(int8_t, gt)[][3][N] =\n+{\n+ {\n+ { 127 },\n+ {\n+ 0, 0, 0, 0,\n+ -1, -1, -1, -1,\n+ 127, 127, 127, 127,\n+ -128, -128, -128, -128,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+ {\n+ { -1 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ -2, -2, -2, -2,\n+ -128, -128, -128, -128,\n+ },\n+ {\n+ 1, 1, 1, 1,\n+ 1, 1, 1, 1,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n+int16_t TEST_BINARY_DATA(int16_t, gt)[][3][N] =\n+{\n+ {\n+ { 32767 },\n+ {\n+ 0, 0, 0, 0,\n+ -1, -1, -1, -1,\n+ 32767, 32767, 32767, 32767,\n+ -32768, -32768, -32768, -32768,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+ {\n+ { -1 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ -2, -2, -2, -2,\n+ -32768, -32768, -32768, -32768,\n+ },\n+ {\n+ 1, 1, 1, 1,\n+ 1, 1, 1, 1,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n+int32_t TEST_BINARY_DATA(int32_t, gt)[][3][N] =\n+{\n+ {\n+ { 2147483647 },\n+ {\n+ 0, 0, 0, 0,\n+ -1, -1, -1, -1,\n+ 2147483647, 2147483647, 2147483647, 2147483647,\n+ -2147483648, -2147483648, -2147483648, -2147483648,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+ {\n+ { -1 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ -2, -2, -2, -2,\n+ -2147483648, -2147483648, -2147483648, -2147483648,\n+ },\n+ {\n+ 1, 1, 1, 1,\n+ 1, 1, 1, 1,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n+int64_t TEST_BINARY_DATA(int64_t, gt)[][3][N] =\n+{\n+ {\n+ { 9223372036854775807ll },\n+ {\n+ 0, 0, 0, 0,\n+ -1, -1, -1, -1,\n+ 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll,\n+ -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,\n+ },\n+ {\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+ {\n+ { -1 },\n+ {\n+ 0, 0, 0, 0,\n+ 1, 1, 1, 1,\n+ -2, -2, -2, -2,\n+ -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,\n+ },\n+ {\n+ 1, 1, 1, 1,\n+ 1, 1, 1, 1,\n+ 0, 0, 0, 0,\n+ 0, 0, 0, 0,\n+ },\n+ },\n+};\n+\n #endif\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c\nnew file mode 100644\nindex 00000000000..0c5c8bbe63d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T int16_t\n+#define NAME gt\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c\nnew file mode 100644\nindex 00000000000..239f029675b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T int32_t\n+#define NAME gt\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c\nnew file mode 100644\nindex 00000000000..fbc59bf6e8c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T int64_t\n+#define NAME gt\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c\nnew file mode 100644\nindex 00000000000..1fe1dbeaf29\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c\n@@ -0,0 +1,15 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-std=c99 --param=gpr2vr-cost=0\" } */\n+\n+#include \"vx_binary.h\"\n+#include \"vx_binary_data.h\"\n+\n+#define T int8_t\n+#define NAME gt\n+\n+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)\n+\n+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)\n+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)\n+\n+#include \"vx_binary_run.h\"\n","prefixes":["v1","2/2"]}