{"id":2233386,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2233386/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260506092124.2542192-1-stefansf@linux.ibm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260506092124.2542192-1-stefansf@linux.ibm.com>","date":"2026-05-06T09:21:24","name":"lra: Reloading section anchors","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"db5561b8b899ec0b5ad7d36c94be2d36a7fbdf27","submitter":{"id":78338,"url":"http://patchwork.ozlabs.org/api/1.1/people/78338/?format=json","name":"Stefan Schulze Frielinghaus","email":"stefansf@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260506092124.2542192-1-stefansf@linux.ibm.com/mbox/","series":[{"id":502960,"url":"http://patchwork.ozlabs.org/api/1.1/series/502960/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502960","date":"2026-05-06T09:21:24","name":"lra: Reloading section anchors","version":1,"mbox":"http://patchwork.ozlabs.org/series/502960/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233386/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233386/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=gkfWYOzt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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b=gkfWYOztW+9v38zjjWfqQgZn2r80OD/xtBBnKkVADv91Ab3yf4G+9DGis\n PkDBtAAxn2suf/8l6GAzIXfzCHVks4oqSgTiU6uP4WjpplKRK8+OGhCT9IlRUG1T\n zyJu+UXFQDCdoCgOs/tbhcRmLvTTpBMdM4CRGGCV+pPdNGktrXtbrV8OfPCmIrVT\n ek5YUjh8924eE6h7/FhzEWJUHqbUIYDZr/WeoyGBlI4hLpFGmMR5lgf1vocpdXZ+\n H/floLAkQgcgrqKuIhTljKC3WilVy59HfZj1VXK8hX8uIuLapTmtyzpPQoUlKZKI\n 298jkLccn/pZDDLlx8rH3ZXfEkmhw==","From":"Stefan Schulze Frielinghaus ","To":"Vladimir Makarov , gcc-patches@gcc.gnu.org","Cc":"Stefan Schulze Frielinghaus ","Subject":"[PATCH] lra: Reloading section anchors","Date":"Wed, 6 May 2026 11:21:24 +0200","Message-ID":"<20260506092124.2542192-1-stefansf@linux.ibm.com>","X-Mailer":"git-send-email 2.53.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNTA2MDA4OCBTYWx0ZWRfX+qwpldlMGuc1\n 91GdKRreRou+7EW0fjBIAqlxgFGh2jZdlkDLYd1FDdLFl5hF3Mn8UOkT31E7aVA3jQ4+wQh+EN4\n WqOQj84C4LrnalmZUw6GW6ASO6ILZ6/TlrH7VOrZuT2KZCj2KXpGHhyYpNO9lO32hJy0Ex2Db0b\n cy/8mzrtqPboyfTafKubsICEI5+XcsEcX5pieT7u0XXKl2K7dLIPF+r/kdNyCzhv2/CTJpw4ZiD\n isVHG6kgu1dP4JQDqGHwbEZbK9liMotwN8OoupYx2M7lTmpnjy3pTp/90LfprczYuJvYDG2Lzjg\n crlFhwOQqvL0OQHQ+30nnDQhVTc7eUu71z9irXpKOxZGy3pfSq9PM53HD45/lKxa9Uly4PxMtsB\n iGSJREPNwFMf4Bmv+2ZwcxRyks2tVBA6TYM3M/yty+Itc70Sp3aCu+iTl5dbduzFGXap/tIwF3Y\n ALI7RV31qVghnGgaZFw==","X-Proofpoint-ORIG-GUID":"srLO44U4KcPNzIDbrvOOEqzTWYwHnt6K","X-Proofpoint-GUID":"srLO44U4KcPNzIDbrvOOEqzTWYwHnt6K","X-Authority-Analysis":"v=2.4 cv=ctWrVV4i c=1 sm=1 tr=0 ts=69fb082a cx=c_pps\n a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17\n a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22\n a=V8glGbnc2Ofi9Qvn3v5h:22 a=mDV3o1hIAAAA:8 a=ydF0yO2sR2PL8jc0SGAA:9","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-05_03,2026-04-30_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015\n suspectscore=0 impostorscore=0 spamscore=0 malwarescore=0 phishscore=0\n bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2605060088","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Stefan Schulze Frielinghaus \n\nCurrently an \"entire\" address is reloaded even in cases where section\nanchors are involved. This makes it harder to share section anchors\nwhich is the whole point of them. For example, in cases where\noffsetable MEMs are ok do not reload .LANCHOR42+offset but only\n.LANCHOR42 and replace the address with the resulting reload register\nand the offset. As a consequence subsequent passes only have to deal\nwith register equivalences in order to share section anchors. For\nexample\n\ndouble x;\ndouble y;\n\ndouble foo ()\n{\n return x + y;\n}\n\nWith this patch, after LRA we have\n\n 20: %r1:DI=`*.LANCHOR0'\n 17: %f0:DF=[%r1:DI]\n 19: %r1:DI=`*.LANCHOR0'\n 12: {%f0:DF=%f0:DF+[%r1:DI+0x8];clobber %cc:CC;}\n\nand after postreload\n\n 20: %r1:DI=`*.LANCHOR0'\n 17: %f0:DF=[%r1:DI]\n 12: {%f0:DF=%f0:DF+[%r1:DI+0x8];clobber %cc:CC;}\n\nOf course, this was a lucky case since both reloads referred to the very\nsame register which allows for trivial removal of insn 19. At least in\ncases like demonstrated by the new test section-anchors-4.c we are\nguaranteed to re-use the reload for a single insn.\n\nBefore testing this patch for multiple targets, I'm wondering whether\nthere is even a way to re-use reloads during LRA across insns (like an\nequiv) such that we wouldn't depend on subsequent passes?\n---\n gcc/lra-constraints.cc | 30 +++++++++++++++++++\n .../gcc.target/s390/section-anchors-4.c | 25 ++++++++++++++++\n 2 files changed, 55 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/s390/section-anchors-4.c","diff":"diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc\nindex ccd68efc956..6779dfee020 100644\n--- a/gcc/lra-constraints.cc\n+++ b/gcc/lra-constraints.cc\n@@ -4839,6 +4839,36 @@ curr_insn_transform (bool check_only_p)\n \t new_reg = emit_inc (rclass, *loc,\n \t\t\t\t/* This value does not matter for MODIFY. */\n \t\t\t\tGET_MODE_SIZE (GET_MODE (op)));\n+\t /* Try to pull out section anchors. For example, instead of\n+\t reloading an \"entire\" address like .LANCHOR42+offset only reload\n+\t .LANCHOR42 and use the new reload register as the base register.\n+\t This allows following optimizations to share section anchors and\n+\t remove redundant loads. */\n+\t else if (GET_CODE (*loc) == CONST\n+\t\t && GET_CODE (XEXP (*loc, 0)) == PLUS\n+\t\t && GET_CODE (XEXP (XEXP (*loc, 0), 0)) == SYMBOL_REF\n+\t\t && SYMBOL_REF_ANCHOR_P (XEXP (XEXP (*loc, 0), 0))\n+\t\t && CONST_INT_P (XEXP (XEXP (*loc, 0), 1))\n+\t\t /* Some offsets are valid in conjunction with a symbol and\n+\t\t invalid in conjunction with a register. Thus, pull out\n+\t\t the anchor only in case the offset is a valid anchor\n+\t\t offset. */\n+\t\t && INTVAL (XEXP (XEXP (*loc, 0), 1))\n+\t\t >= targetm.min_anchor_offset\n+\t\t && INTVAL (XEXP (XEXP (*loc, 0), 1))\n+\t\t <= targetm.max_anchor_offset)\n+\t {\n+\t rtx anchor = XEXP (XEXP (*loc, 0), 0);\n+\t rtx offset = XEXP (XEXP (*loc, 0), 1);\n+\n+\t if (get_reload_reg (OP_IN, Pmode, anchor, rclass,\n+\t\t\t\t NULL, false, false,\n+\t\t\t\t \"offsetable address\", &new_reg))\n+\t\t lra_emit_move (new_reg, anchor);\n+\n+\t\tnew_reg = gen_rtx_PLUS (Pmode, new_reg, offset);\n+\t\tlra_assert (valid_address_p (Pmode, new_reg, MEM_ADDR_SPACE (op)));\n+\t }\n \t else if (get_reload_reg (OP_IN, Pmode, *loc, rclass,\n \t\t\t\t NULL, false, false,\n \t\t\t\t \"offsetable address\", &new_reg))\ndiff --git a/gcc/testsuite/gcc.target/s390/section-anchors-4.c b/gcc/testsuite/gcc.target/s390/section-anchors-4.c\nnew file mode 100644\nindex 00000000000..0b4cd081c61\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/s390/section-anchors-4.c\n@@ -0,0 +1,25 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -fdump-rtl-ira-slim -fdump-rtl-reload-slim\" } */\n+/* { dg-final { scan-assembler-times \"\\tlarl\\t\" 1 } } */\n+/* { dg-final { scan-rtl-dump \"%cc:CCZ=cmp\\\\\\(\\\\\\[`\\\\\\*.LANCHOR0'\\\\\\],\\\\\\[const\\\\\\(`\\\\\\*.LANCHOR0'\\\\\\+0x8\\\\\\)\\\\\\]\\\\\\)\" \"ira\" } } */\n+/* { dg-final { scan-rtl-dump \"%cc:CCZ=cmp\\\\\\(\\\\\\[(%r\\[1-9\\]\\[0-9\\]?):DI\\\\\\],\\\\\\[\\\\1:DI\\\\\\+0x8\\\\\\]\\\\\\)\" \"reload\" } } */\n+\n+/* Ensure that we get the same reload register for the second memory operand.\n+ Prior LRA we have\n+\n+ 55: %cc:CCZ=cmp([`*.LANCHOR0'],[const(`*.LANCHOR0'+0x8)])\n+\n+ and after LRA\n+\n+ 59: %r1:DI=`*.LANCHOR0'\n+ 55: %cc:CCZ=cmp([%r1:DI],[%r1:DI+0x8]) */\n+\n+long x, y;\n+\n+long\n+foo (void)\n+{\n+ if (x == y)\n+ return 42;\n+ return 0;\n+}\n","prefixes":[]}