{"id":2233275,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2233275/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506031942.251335-3-junjie.cao@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260506031942.251335-3-junjie.cao@intel.com>","date":"2026-05-06T03:19:42","name":"[v3,2/2] tests/qtest: add 8-byte MMIO access sweep for intel-iommu","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9befa3fc0eeec88a18fbb708e356a0e4b8634c11","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/1.1/people/91537/?format=json","name":"Junjie Cao","email":"junjie.cao@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506031942.251335-3-junjie.cao@intel.com/mbox/","series":[{"id":502919,"url":"http://patchwork.ozlabs.org/api/1.1/series/502919/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502919","date":"2026-05-06T03:19:41","name":"[v3,1/2] intel_iommu: fix guest-triggerable abort on oversized MMIO access","version":3,"mbox":"http://patchwork.ozlabs.org/series/502919/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233275/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233275/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=VbuAF1Cc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 05 May 2026 23:20:25 -0400","from fmviesa006.fm.intel.com ([10.60.135.146])\n by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 May 2026 20:20:22 -0700","from junjie-desk-dev.bj.intel.com ([10.238.152.71])\n by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 May 2026 20:20:19 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1778037623; x=1809573623;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=wItBfHW6v9wsyjtAKVgJYEePhRBXmoutUyn+sJKbZ/w=;\n b=VbuAF1CcxL4WRgdwCnGnRXxRMrb7V/L+mBACtOOFEA2Nn8g2OjIWAcHO\n ejlYtc6ss0tA0W7aMvHrIb21bzVYWKf6sgx+VPPjgl6V4vq68/9W6l8tn\n 2ech70LytiyfMYznTMbKyDci0ek34rpwgB97UvvOhqrpHDoihDiDmZN57\n POQQTX3RzlLzY9QLD7OH4sJXS9JZz7L7HdRI7AfVsmuccF3dKnBUxd/fG\n DCe/Qtn+w1M4VJgqRNJztfS5OR17jeAl29AE/TEKy5PJ7Vn8sqptIMo0A\n 1fUhX4s+ju32s1XxdGb1EbrGyBSVS3LRueu5X2sEid3RtiE7ltdFr4Wu6 A==;","X-CSE-ConnectionGUID":["YQu2PSAtQXmlxCrhAVcSeg==","lPWmmaJSTFmsp7PBRX3IZg=="],"X-CSE-MsgGUID":["NoQiF7q3R4S4DiT5jYsalw==","5OLvUpkDRLKC+XWB47r2/A=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11777\"; a=\"78783065\"","E=Sophos;i=\"6.23,218,1770624000\"; d=\"scan'208\";a=\"78783065\"","E=Sophos;i=\"6.23,218,1770624000\"; d=\"scan'208\";a=\"231417016\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"qemu-devel@nongnu.org","Cc":"junjie.cao@intel.com, zhenzhong.duan@intel.com, philmd@linaro.org,\n mst@redhat.com, jasowang@redhat.com, yi.l.liu@intel.com,\n clement.mathieu--drif@bull.com, marcel.apfelbaum@gmail.com,\n pbonzini@redhat.com, richard.henderson@linaro.org, farosas@suse.de,\n lvivier@redhat.com","Subject":"[PATCH v3 2/2] tests/qtest: add 8-byte MMIO access sweep for\n intel-iommu","Date":"Wed, 6 May 2026 11:19:42 +0800","Message-ID":"<20260506031942.251335-3-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"\n ","References":"\n ","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=192.198.163.17;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-47","X-Spam_score":"-4.8","X-Spam_bar":"----","X-Spam_report":"(-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.443,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Sweep every 4-byte-aligned offset in the VT-d MMIO register space\nwith 8-byte reads and writes to verify that no register handler\naborts on an oversized access.\n\nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Junjie Cao \n---\n tests/qtest/intel-iommu-test.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)","diff":"diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c\nindex e5cc6acaf0..b1763ed294 100644\n--- a/tests/qtest/intel-iommu-test.c\n+++ b/tests/qtest/intel-iommu-test.c\n@@ -17,11 +17,39 @@\n #define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \\\n VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FSTS)\n \n+static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset)\n+{\n+ return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);\n+}\n+\n static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)\n {\n return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);\n }\n \n+static inline void vtd_reg_writeq(QTestState *s, uint64_t offset,\n+ uint64_t value)\n+{\n+ qtest_writeq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset, value);\n+}\n+\n+static void test_intel_iommu_8byte_access(void)\n+{\n+ QTestState *s;\n+ uint64_t off;\n+\n+ s = qtest_init(\"-M q35 -device intel-iommu\");\n+\n+ for (off = 0; off < DMAR_REG_SIZE; off += 4) {\n+ vtd_reg_readq(s, off);\n+ vtd_reg_writeq(s, off, 0);\n+ }\n+\n+ g_assert_cmpuint(vtd_reg_readl(s, DMAR_VER_REG), !=, 0);\n+\n+ qtest_quit(s);\n+}\n+\n static void test_intel_iommu_stage_1(void)\n {\n uint8_t init_csr[DMAR_REG_SIZE]; /* register values */\n@@ -58,6 +86,8 @@ static void test_intel_iommu_stage_1(void)\n int main(int argc, char **argv)\n {\n g_test_init(&argc, &argv, NULL);\n+ qtest_add_func(\"/q35/intel-iommu/8byte-access\",\n+ test_intel_iommu_8byte_access);\n qtest_add_func(\"/q35/intel-iommu/stage-1\", test_intel_iommu_stage_1);\n \n return g_test_run();\n","prefixes":["v3","2/2"]}