{"id":2233274,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2233274/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506031942.251335-2-junjie.cao@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260506031942.251335-2-junjie.cao@intel.com>","date":"2026-05-06T03:19:41","name":"[v3,1/2] intel_iommu: fix guest-triggerable abort on oversized MMIO access","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dcbb3fff9604307708a8b06aba6bf8a5386b9d93","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/1.1/people/91537/?format=json","name":"Junjie Cao","email":"junjie.cao@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506031942.251335-2-junjie.cao@intel.com/mbox/","series":[{"id":502919,"url":"http://patchwork.ozlabs.org/api/1.1/series/502919/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502919","date":"2026-05-06T03:19:41","name":"[v3,1/2] intel_iommu: fix guest-triggerable abort on oversized MMIO access","version":3,"mbox":"http://patchwork.ozlabs.org/series/502919/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233274/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233274/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=mcljC2R6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=\"78783049\"","E=Sophos;i=\"6.23,218,1770624000\"; d=\"scan'208\";a=\"78783049\"","E=Sophos;i=\"6.23,218,1770624000\"; d=\"scan'208\";a=\"231417005\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"qemu-devel@nongnu.org","Cc":"junjie.cao@intel.com, zhenzhong.duan@intel.com, philmd@linaro.org,\n mst@redhat.com, jasowang@redhat.com, yi.l.liu@intel.com,\n clement.mathieu--drif@bull.com, marcel.apfelbaum@gmail.com,\n pbonzini@redhat.com, richard.henderson@linaro.org, farosas@suse.de,\n lvivier@redhat.com","Subject":"[PATCH v3 1/2] intel_iommu: fix guest-triggerable abort on oversized\n MMIO access","Date":"Wed, 6 May 2026 11:19:41 +0800","Message-ID":"<20260506031942.251335-2-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"\n ","References":"\n ","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=192.198.163.17;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-47","X-Spam_score":"-4.8","X-Spam_bar":"----","X-Spam_report":"(-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.443,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"An 8-byte guest access to a 32-bit-only VT-d register hit\nassert(size == 4) and aborted QEMU. Remove all 25 asserts.\n\n21 sit at non-8-byte-aligned offsets and are rejected by\nmemory_region_access_valid() before reaching the handler -- dead\ncode, simply deleted.\n\nThe remaining 4 guard 8-byte-aligned 32-bit registers reachable\nby a well-formed 8-byte access (FECTL 0x38, IECTL 0xa0, IEADDR\n0xa8, PECTL 0xe0). Writes fall through to vtd_set_long(), which\ntakes uint32_t and implicitly truncates, and log a guest error.\nReads fall through to the default vtd_get_quad() -- equivalent\nto two 4-byte reads and therefore harmless, no warn needed.\nmin_access_size stays 4, so all size-based branches on 64-bit\nregister pairs are preserved.\n\nFound by generic-fuzz (24 distinct crash seeds, all fixed).\n\nSuggested-by: Zhenzhong Duan \nSigned-off-by: Junjie Cao \n---\n hw/i386/intel_iommu.c | 41 ++++++++++++++++-------------------------\n 1 file changed, 16 insertions(+), 25 deletions(-)","diff":"diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex f395fa248c..0fb89332f9 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -3713,7 +3713,6 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n break;\n \n case DMAR_RTADDR_REG_HI:\n- assert(size == 4);\n val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n break;\n \n@@ -3728,12 +3727,10 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n break;\n \n case DMAR_IQA_REG_HI:\n- assert(size == 4);\n val = s->iq >> 32;\n break;\n \n case DMAR_PEUADDR_REG:\n- assert(size == 4);\n val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);\n break;\n \n@@ -3779,7 +3776,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_CCMD_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_ccmd_write(s);\n break;\n@@ -3795,13 +3791,11 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IOTLB_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_iotlb_write(s);\n break;\n \n case DMAR_PEUADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3815,27 +3809,27 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IVA_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Fault Status Register, 32-bit */\n case DMAR_FSTS_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_fsts_write(s);\n break;\n \n /* Fault Event Control Register, 32-bit */\n case DMAR_FECTL_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n+ \"addr=0x%\" PRIx64, __func__, size, addr);\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_fectl_write(s);\n break;\n \n /* Fault Event Data Register, 32-bit */\n case DMAR_FEDATA_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3854,13 +3848,11 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n \n /* Fault Event Upper Address Register, 32-bit */\n case DMAR_FEUADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Protected Memory Enable Register, 32-bit */\n case DMAR_PMEN_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3874,7 +3866,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_RTADDR_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3889,7 +3880,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IQT_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n /* 19:63 of IQT_REG is RsvdZ, do nothing here */\n break;\n@@ -3905,39 +3895,41 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IQA_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Completion Status Register, 32-bit */\n case DMAR_ICS_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_ics_write(s);\n break;\n \n /* Invalidation Event Control Register, 32-bit */\n case DMAR_IECTL_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n+ \"addr=0x%\" PRIx64, __func__, size, addr);\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_iectl_write(s);\n break;\n \n /* Invalidation Event Data Register, 32-bit */\n case DMAR_IEDATA_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Event Address Register, 32-bit */\n case DMAR_IEADDR_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n+ \"addr=0x%\" PRIx64, __func__, size, addr);\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Event Upper Address Register, 32-bit */\n case DMAR_IEUADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3951,7 +3943,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_FRCD_REG_0_1:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3966,7 +3957,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_FRCD_REG_0_3:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n /* May clear bit 127 (Fault), update PPF */\n vtd_update_fsts_ppf(s);\n@@ -3981,18 +3971,19 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IRTA_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n case DMAR_PRS_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_prs_write(s);\n break;\n \n case DMAR_PECTL_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n+ \"addr=0x%\" PRIx64, __func__, size, addr);\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_pectl_write(s);\n break;\n","prefixes":["v3","1/2"]}