{"id":2232513,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2232513/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-9-232a648e63c6@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260504-feat-mte4-v5-9-232a648e63c6@gmail.com>","date":"2026-05-04T15:50:42","name":"[v5,09/15] target/arm: load on canonical tag loads ext bits","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"664b430f8411684a23cfbd6ac5cb786bfc71e6c5","submitter":{"id":91863,"url":"http://patchwork.ozlabs.org/api/1.1/people/91863/?format=json","name":"Gabriel Brookman","email":"brookmangabriel@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-9-232a648e63c6@gmail.com/mbox/","series":[{"id":502688,"url":"http://patchwork.ozlabs.org/api/1.1/series/502688/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688","date":"2026-05-04T15:50:33","name":"target/arm: add support for MTE4","version":5,"mbox":"http://patchwork.ozlabs.org/series/502688/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232513/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232513/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ZvOQttqB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260504-feat-mte4-v5-9-232a648e63c6@gmail.com>","References":"<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>","In-Reply-To":"<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Peter Maydell ,\n Gustavo Romero ,\n Richard Henderson , qemu-arm@nongnu.org,\n Laurent Vivier ,\n Gabriel Brookman , Helge Deller ,\n Pierrick Bouvier ,\n Pierrick Bouvier ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777909867; l=5681;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=Ws2Tqe13fBijY+IHknD2CyebZv1in1ArUctH8Hio2sA=;\n b=oz8eYjE5Vhv9ZTARi40/Hp4hw9BTP367GpMsUgRMbeoVgKXesDUDsrV4q+eHUAoXCN10U4XKi\n TjEmXWkKoGZCOfw5lW6i1VHoDaYhtfJGVF+zbu/NgSZ3rybx9vBpuSW","X-Developer-Key":"i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=","Received-SPF":"pass client-ip=2607:f8b0:4864:20::830;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x830.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Loading tags from canonically tagged regions should use the canonical\ntags (extension bits), not allocation tags. See AArch64_MemTagRead().\n\nSigned-off-by: Gabriel Brookman \n---\n target/arm/tcg/helper-a64-defs.h | 4 ++--\n target/arm/tcg/mte_helper.c | 42 +++++++++++++++++++++++++++++++++++++---\n target/arm/tcg/translate-a64.c | 4 ++--\n 3 files changed, 43 insertions(+), 7 deletions(-)","diff":"diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h\nindex 3c3c5dddb7..c08c8c3991 100644\n--- a/target/arm/tcg/helper-a64-defs.h\n+++ b/target/arm/tcg/helper-a64-defs.h\n@@ -102,14 +102,14 @@ DEF_HELPER_FLAGS_3(mte_check, TCG_CALL_NO_WG, i64, env, i32, i64)\n DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64)\n DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)\n DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32)\n-DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64)\n+DEF_HELPER_FLAGS_4(ldg, TCG_CALL_NO_WG, i64, env, i64, i64, i32)\n DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64)\n DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64)\n DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64)\n DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64)\n DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64)\n DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64)\n-DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64)\n+DEF_HELPER_FLAGS_3(ldgm, TCG_CALL_NO_WG, i64, env, i64, i32)\n DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64)\n DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64)\n \ndiff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c\nindex d35e3ef04d..8ed31ca2d8 100644\n--- a/target/arm/tcg/mte_helper.c\n+++ b/target/arm/tcg/mte_helper.c\n@@ -304,7 +304,7 @@ int load_tag1(uint64_t ptr, uint8_t *mem)\n return extract32(*mem, ofs, 4);\n }\n \n-uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)\n+uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx)\n {\n int mmu_idx = arm_env_mmu_index(env);\n uint8_t *mem;\n@@ -317,6 +317,11 @@ uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)\n /* Load if page supports tags. */\n if (mem) {\n rtag = load_tag1(ptr, mem);\n+ } else {\n+ uint64_t bit55 = extract64(ptr, 55, 1);\n+ if (mtx) {\n+ rtag = 0xF * bit55;\n+ }\n }\n \n return address_with_allocation_tag(xt, rtag);\n@@ -458,17 +463,19 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)\n }\n }\n \n-uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)\n+uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr, uint32_t mtx)\n {\n int mmu_idx = arm_env_mmu_index(env);\n uintptr_t ra = GETPC();\n int gm_bs = env_archcpu(env)->gm_blocksize;\n int gm_bs_bytes = 4 << gm_bs;\n void *tag_mem;\n- uint64_t ret;\n+ uint64_t ret, canonical_tag_val;\n int shift;\n+ bool bit55;\n \n ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);\n+ bit55 = extract64(ptr, 55, 1);\n \n /* Trap if accessing an invalid page. */\n tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,\n@@ -476,6 +483,35 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)\n \n /* The tag is squashed to zero if the page does not support tags. */\n if (!tag_mem) {\n+ /* Load canonical value if mtx is set (untagged memory region) */\n+ if (mtx) {\n+ canonical_tag_val = -(uint64_t)bit55;\n+ switch (gm_bs) {\n+ case 3:\n+ /* 32 bytes -> 2 tags -> 8 result bits */\n+ ret = (uint8_t)canonical_tag_val;\n+ break;\n+ case 4:\n+ /* 64 bytes -> 4 tags -> 16 result bits */\n+ ret = (uint16_t)canonical_tag_val;\n+ break;\n+ case 5:\n+ /* 128 bytes -> 8 tags -> 32 result bits */\n+ ret = (uint32_t)canonical_tag_val;\n+ break;\n+ case 6:\n+ /* 256 bytes -> 16 tags -> 64 result bits */\n+ return canonical_tag_val;\n+ default:\n+ /*\n+ * CPU configured with unsupported/invalid gm blocksize.\n+ * This is detected early in arm_cpu_realizefn.\n+ */\n+ g_assert_not_reached();\n+ }\n+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;\n+ return ret << shift;\n+ }\n return 0;\n }\n \ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex cd86178d56..5fbc54de4b 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -4711,7 +4711,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)\n tcg_rt = cpu_reg(s, a->rt);\n \n if (s->ata[0]) {\n- gen_helper_ldgm(tcg_rt, tcg_env, addr);\n+ gen_helper_ldgm(tcg_rt, tcg_env, addr, tcg_constant_i32(s->mtx));\n } else {\n MMUAccessType acc = MMU_DATA_LOAD;\n int size = 4 << s->gm_blocksize;\n@@ -4746,7 +4746,7 @@ static bool trans_LDG(DisasContext *s, arg_ldst_tag *a)\n tcg_gen_andi_i64(addr, addr, -TAG_GRANULE);\n tcg_rt = cpu_reg(s, a->rt);\n if (s->ata[0]) {\n- gen_helper_ldg(tcg_rt, tcg_env, addr, tcg_rt);\n+ gen_helper_ldg(tcg_rt, tcg_env, addr, tcg_rt, tcg_constant_i32(s->mtx));\n } else {\n /*\n * Tag access disabled: we must check for aborts on the load\n","prefixes":["v5","09/15"]}