{"id":2232509,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2232509/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-4-232a648e63c6@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260504-feat-mte4-v5-4-232a648e63c6@gmail.com>","date":"2026-05-04T15:50:37","name":"[v5,04/15] linux-user: add MTE_STORE_ONLY to prctl","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e542c40d4421c65b863adaefebf5cdd8942f83b9","submitter":{"id":91863,"url":"http://patchwork.ozlabs.org/api/1.1/people/91863/?format=json","name":"Gabriel Brookman","email":"brookmangabriel@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-4-232a648e63c6@gmail.com/mbox/","series":[{"id":502688,"url":"http://patchwork.ozlabs.org/api/1.1/series/502688/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688","date":"2026-05-04T15:50:33","name":"target/arm: add support for MTE4","version":5,"mbox":"http://patchwork.ozlabs.org/series/502688/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232509/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232509/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=jtuyI9dx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260504-feat-mte4-v5-4-232a648e63c6@gmail.com>","References":"<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>","In-Reply-To":"<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Peter Maydell ,\n Gustavo Romero ,\n Richard Henderson , qemu-arm@nongnu.org,\n Laurent Vivier ,\n Gabriel Brookman , Helge Deller ,\n Pierrick Bouvier ,\n Pierrick Bouvier ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777909867; l=4942;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=3NUHlDKCw8l8rqmAwbaWm0eM8fht4yd8LR/eAfpLXkM=;\n b=qaor9hF4vUH0Y5C2PSDNFkZo239y6H4EkDjtaT+bpxkAmJpegOR/RoWzOFUD//lvnAR06k1IT\n UOZq0fombvQCtuNPHUdjUQOLxo7Ah0nYTB/H+S1kA0CXy2N1Zox78yQ","X-Developer-Key":"i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=","Received-SPF":"pass client-ip=2607:f8b0:4864:20::82c;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x82c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Linux-user processes can now control whether MTE_STORE_ONLY is enabled\nusing the prctl syscall.\n\nSigned-off-by: Gabriel Brookman \nReviewed-by: Richard Henderson \n---\n linux-user/aarch64/mte_user_helper.c | 11 ++++++++++-\n linux-user/aarch64/mte_user_helper.h | 14 +++++++++-----\n linux-user/aarch64/target_prctl.h | 6 +++++-\n target/arm/gdbstub64.c | 2 +-\n tests/tcg/aarch64/mte.h | 3 +++\n 5 files changed, 28 insertions(+), 8 deletions(-)","diff":"diff --git a/linux-user/aarch64/mte_user_helper.c b/linux-user/aarch64/mte_user_helper.c\nindex a5b1c8503b..b5c4dafcda 100644\n--- a/linux-user/aarch64/mte_user_helper.c\n+++ b/linux-user/aarch64/mte_user_helper.c\n@@ -10,7 +10,7 @@\n #include \"qemu.h\"\n #include \"mte_user_helper.h\"\n \n-void arm_set_mte_tcf0(CPUArchState *env, abi_long value)\n+void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value)\n {\n /*\n * Write PR_MTE_TCF to SCTLR_EL1[TCF0].\n@@ -32,4 +32,13 @@ void arm_set_mte_tcf0(CPUArchState *env, abi_long value)\n tcf = 2;\n }\n env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);\n+\n+ /*\n+ * If MTE_STORE_ONLY is enabled, set the corresponding sctlr_el1 bit\n+ */\n+ if (value & PR_MTE_STORE_ONLY) {\n+ env->cp15.sctlr_el[1] |= SCTLR_TCSO0;\n+ } else {\n+ env->cp15.sctlr_el[1] &= ~SCTLR_TCSO0;\n+ }\n }\ndiff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_user_helper.h\nindex 0c53abda22..8a46f743f4 100644\n--- a/linux-user/aarch64/mte_user_helper.h\n+++ b/linux-user/aarch64/mte_user_helper.h\n@@ -20,15 +20,19 @@\n # define PR_MTE_TAG_SHIFT 3\n # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)\n #endif\n+#ifndef PR_MTE_STORE_ONLY\n+# define PR_MTE_STORE_ONLY (1UL << 19)\n+#endif\n \n /**\n- * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register\n+ * arm_set_tagged_addr_ctrl - Set TCF0 and TCSO0 fields in SCTLR_EL1 register\n * @env: The CPU environment\n- * @value: The value to be set for the Tag Check Fault in EL0 field.\n+ * @value: The value to be set for the Tag Check Fault and Tag Check Store Only\n+ * in EL0 field.\n *\n- * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC\n- * mode is selected instead. So, there is no way to set the ASYMM mode.\n+ * Only SYNC and ASYNC modes can be selected for TCF0. If ASYMM mode is given,\n+ * the SYNC mode is selected instead. So, there is no way to set the ASYMM mode.\n */\n-void arm_set_mte_tcf0(CPUArchState *env, abi_long value);\n+void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value);\n \n #endif /* AARCH64_MTE_USER_HELPER_H */\ndiff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h\nindex 621be5727f..d91e75d60d 100644\n--- a/linux-user/aarch64/target_prctl.h\n+++ b/linux-user/aarch64/target_prctl.h\n@@ -168,6 +168,9 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)\n if (cpu_isar_feature(aa64_mte, cpu)) {\n valid_mask |= PR_MTE_TCF_MASK;\n valid_mask |= PR_MTE_TAG_MASK;\n+ if (cpu_isar_feature(aa64_mte_store_only, cpu)) {\n+ valid_mask |= PR_MTE_STORE_ONLY;\n+ }\n }\n \n if (arg2 & ~valid_mask) {\n@@ -176,7 +179,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)\n env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;\n \n if (cpu_isar_feature(aa64_mte, cpu)) {\n- arm_set_mte_tcf0(env, arg2);\n+ arm_set_tagged_addr_ctrl(env, arg2);\n \n /*\n * Write PR_MTE_TAG to GCR_EL1[Exclude].\n@@ -185,6 +188,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)\n */\n env->cp15.gcr_el1 =\n deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT);\n+\n arm_rebuild_hflags(env);\n }\n return 0;\ndiff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c\nindex a4fa740caf..0c3e5b30bd 100644\n--- a/target/arm/gdbstub64.c\n+++ b/target/arm/gdbstub64.c\n@@ -684,7 +684,7 @@ int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg)\n * expose options regarding the type of MTE fault that can be controlled at\n * runtime.\n */\n- arm_set_mte_tcf0(env, tcf);\n+ arm_set_tagged_addr_ctrl(env, tcf);\n \n return 1;\n #else\ndiff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h\nindex 0805676b11..17b932f3f1 100644\n--- a/tests/tcg/aarch64/mte.h\n+++ b/tests/tcg/aarch64/mte.h\n@@ -20,6 +20,9 @@\n #ifndef PR_TAGGED_ADDR_ENABLE\n # define PR_TAGGED_ADDR_ENABLE (1UL << 0)\n #endif\n+#ifndef PR_MTE_STORE_ONLY\n+# define PR_MTE_STORE_ONLY (1UL << 19)\n+#endif\n #ifndef PR_MTE_TCF_SHIFT\n # define PR_MTE_TCF_SHIFT 1\n # define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)\n","prefixes":["v5","04/15"]}