{"id":2232314,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2232314/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com>","date":"2026-05-04T10:48:42","name":"[v2,1/2] dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b4630f3bd9dc16a5900057ad1a43508a0f5dac83","submitter":{"id":93282,"url":"http://patchwork.ozlabs.org/api/1.1/people/93282/?format=json","name":"Komal Bajaj","email":"komal.bajaj@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com/mbox/","series":[{"id":502642,"url":"http://patchwork.ozlabs.org/api/1.1/series/502642/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502642","date":"2026-05-04T10:48:41","name":"pinctrl: qcom: Add support for Qualcomm Shikra SoC","version":2,"mbox":"http://patchwork.ozlabs.org/series/502642/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232314/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232314/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=iXIhppIg;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=WiPTwtQX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com>","References":"<20260504-shikra-pinctrl-v2-0-14e9dcc2d685@oss.qualcomm.com>","In-Reply-To":"<20260504-shikra-pinctrl-v2-0-14e9dcc2d685@oss.qualcomm.com>","To":"Bjorn Andersson , Linus Walleij ,\n Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley ,\n Richard Cochran ","Cc":"linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n netdev@vger.kernel.org, Komal Bajaj ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777891727; l=4446;\n i=komal.bajaj@oss.qualcomm.com; s=20250710; h=from:subject:message-id;\n bh=4L9GSadaTqjS847eLA+jgX3kru06L5o3Zua4WBwh3Bs=;\n b=hCr9Bt3CEH+/nEzT5GTj0Qf3eoUBVbeEy5riyuXTkejAUR96lvx1n7PxuNy9rl2ka4dirsAWI\n T/XAjjE5b2FCTwzKYVqkFY0PrUeE3g61WftANgo+R8S9sMf9RNdb7Jo","X-Developer-Key":"i=komal.bajaj@oss.qualcomm.com; a=ed25519;\n pk=wKh8mgDh+ePUZ4IIvpBhQOqf16/KvuQHvSvHK20LXNU=","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNTA0MDExMiBTYWx0ZWRfX0n0dnRespnjN\n fCMkPC4O3FsYMTUdqWJvFGp9vw4ClzvjS+wqztQ5kiZrwjgB1nuTfK7EEvG5jKvOnkejVIvHJWd\n eBrmCby2mzrDb9NWTqW0tnXj9qynWAUfZFEIh88oBLhW+AhHHOLv5hY+GlN1spaZ18KC1C6Zzky\n t2hgmono1wY14UoOaj+Haqh3w8YZnxrxluaelc38p+I2j+RlmZNePjIDZzcgzP/2Uwa84yWITO0\n x80R6FPXc+lPD2mAGEP95G1RenZnrZKZVh+ZN/fnJfcff859koo37SJaG2qunIkkE8hrVT4NZ61\n nqETnpzJYOCFf1ZGQpDPQglYXeC5jZlGAuoSAAkpSoL5i3JEfaChBI86pnaWoXpcOJUnNKGvGeG\n t9268nMB0SPEw8JIfKuJnNn24lsisMWyjJPTGerjfASzY4kQWnzjLAdVn17pTlYlpc4KJLG8HhF\n VfJ8YnP7vOcdGb4w1vw==","X-Proofpoint-ORIG-GUID":"DwImsBkN1qSugWkcqlc2A8TYyJGnyRTz","X-Proofpoint-GUID":"DwImsBkN1qSugWkcqlc2A8TYyJGnyRTz","X-Authority-Analysis":"v=2.4 cv=C47ZDwP+ c=1 sm=1 tr=0 ts=69f87999 cx=c_pps\n a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22\n a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=bT5XQOCXPleopHcqzpYA:9 a=QEXdDO2ut3YA:10\n a=324X-CrmTo6CU4MGRt3R:22 a=sptkURWiP4Gy88Gu7hUp:22","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-04_03,2026-04-30_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 suspectscore=0\n bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040112"},"content":"Add a DeviceTree binding to describe the TLMM block on Qualcomm's\nShikra SoC.\n\nSigned-off-by: Komal Bajaj \n---\n .../bindings/pinctrl/qcom,shikra-tlmm.yaml | 123 +++++++++++++++++++++\n 1 file changed, 123 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml\nnew file mode 100644\nindex 000000000000..411c402f9044\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml\n@@ -0,0 +1,123 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Technologies, Inc. Shikra TLMM block\n+\n+maintainers:\n+ - Komal Bajaj \n+\n+description: |\n+ Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,shikra-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 83\n+\n+ gpio-line-names:\n+ maxItems: 166\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-shikra-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-shikra-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-shikra-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$\"\n+ - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,\n+ sdc2_clk, sdc2_cmd, sdc2_data ]\n+ minItems: 1\n+ maxItems: 36\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,\n+ atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,\n+ cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,\n+ dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,\n+ emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,\n+ emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,\n+ i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,\n+ mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,\n+ nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,\n+ phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,\n+ qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,\n+ qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,\n+ qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,\n+ qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,\n+ ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,\n+ tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,\n+ vfr, vsense_trigger_mirnat, wlan ]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include \n+\n+ tlmm: pinctrl@500000 {\n+ compatible = \"qcom,shikra-tlmm\";\n+ reg = <0x00500000 0x800000>;\n+\n+ interrupts = ;\n+\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+\n+ gpio-ranges = <&tlmm 0 0 166>;\n+\n+ qup-uart0-default-state {\n+ pins = \"gpio0\", \"gpio1\";\n+ function = \"qup0_se1\";\n+ drive-strength = <2>;\n+ bias-disable;\n+ };\n+ };\n+...\n","prefixes":["v2","1/2"]}